[PATCH] D95800: [RISCV] Make scalable vector FMA commutable for register allocation.

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added a comment.

If you wanted to appease the linter you could do something gross like:

  #define CASE_VFMA_OPCODE_COMMON(OP, TYPE, LMUL) \
    RISCV::PseudoV##OP##_##TYPE##_##LMUL##_COMMUTABLE
  
  #define CASE_VFMA_OPCODE_LMULS(OP, TYPE) \
    CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF8): \
    case CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF4): \
    case CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF2): \
    case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M1): \
    case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M2): \
    case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M4): \
    case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M8)
  
  #define CASE_VFMA_SPLATS(OP) \
    CASE_VFMA_OPCODE_LMULS(OP, VF16): \
    case CASE_VFMA_OPCODE_LMULS(OP, VF32): \
    case CASE_VFMA_OPCODE_LMULS(OP, VF64)

(i.e. the leading `case` and trailing `:` are omitted) that you then use as, say:

  case CASE_VFMA_OPCODE_LMULS(FMADD, VV):
  case CASE_VFMA_OPCODE_LMULS(FMSUB, VV):
  case CASE_VFMA_OPCODE_LMULS(FNMADD, VV):
  case CASE_VFMA_OPCODE_LMULS(FNMSUB, VV): {

which is hopefully enough to get it to recognise the macros as case statements. Maybe you can even keep the `case` keyword and it's just the colon that's needed in order to make it look label-ish; if so that's rather nicer (and mirrors how statement macros tend to leave off the final semicolon).


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95800/new/

https://reviews.llvm.org/D95800