[PATCH] D94974: [SLP] Try doubled MaxElts for stores vectorization

[Anton Afanasyev via Phabricator via llvm-commits]

anton-afanasyev added inline comments.


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Comment at: llvm/test/Transforms/SLPVectorizer/X86/arith-mul.ll:183
+; AVX2_PREFER128-NEXT:    [[TMP5:%.*]] = mul <4 x i64> [[TMP1]], [[TMP3]]
+; AVX2_PREFER128-NEXT:    [[TMP6:%.*]] = mul <4 x i64> [[TMP2]], [[TMP4]]
+; AVX2_PREFER128-NEXT:    store <4 x i64> [[TMP5]], <4 x i64>* bitcast ([8 x i64]* @c64 to <4 x i64>*), align 8
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RKSimon wrote:
> We're setting prefer-128-bit and yet still generating <4 x i64> ops?
Hmm, yes, you're right, that's strange to generate `<4 x i64>` for the case with preferable width (=128). But we can't check this at the abstract llvm level. Generally we don't know the target constraints, so this my patch looks too tricky for such cases.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D94974/new/

https://reviews.llvm.org/D94974