[PATCH] D95869: [RISCV] Fix incorrect RVV sdiv/udiv lowering

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck created this revision.
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Due to a clerical error, the sdiv operation was mapping to vdivu and
udiv to vdiv, when the opposite mapping is the correct one.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D95869

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll

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