[llvm] c4fe29e - [ARM] Extra shuffle tests. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 2 06:16:55 PST 2021
Author: David Green
Date: 2021-02-02T14:16:42Z
New Revision: c4fe29e0e5b6f637d12997bbd2b9c7634ae5598f
URL: https://github.com/llvm/llvm-project/commit/c4fe29e0e5b6f637d12997bbd2b9c7634ae5598f
DIFF: https://github.com/llvm/llvm-project/commit/c4fe29e0e5b6f637d12997bbd2b9c7634ae5598f.diff
LOG: [ARM] Extra shuffle tests. NFC
Added:
Modified:
llvm/test/CodeGen/Thumb2/mve-shuffle.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/Thumb2/mve-shuffle.ll b/llvm/test/CodeGen/Thumb2/mve-shuffle.ll
index 40f974fecab1..863ae1e9557e 100644
--- a/llvm/test/CodeGen/Thumb2/mve-shuffle.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-shuffle.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK
-; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK
+; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECKFP
define arm_aapcs_vfpcc <4 x i32> @shuffle1_i32(<4 x i32> %src) {
; CHECK-LABEL: shuffle1_i32:
@@ -59,6 +59,143 @@ entry:
ret <4 x i32> %out
}
+define arm_aapcs_vfpcc <4 x i32> @oneoff11_i32(<4 x i32> %src1, <4 x i32> %src2) {
+; CHECK-LABEL: oneoff11_i32:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov.f32 s2, s1
+; CHECK-NEXT: bx lr
+entry:
+ %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 0, i32 1, i32 1, i32 3>
+ ret <4 x i32> %out
+}
+
+define arm_aapcs_vfpcc <4 x i32> @oneoff12_i32(<4 x i32> %src1, <4 x i32> %src2) {
+; CHECK-LABEL: oneoff12_i32:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov.f32 s5, s1
+; CHECK-NEXT: vmov.f32 s6, s2
+; CHECK-NEXT: vmov.f32 s7, s3
+; CHECK-NEXT: vmov q0, q1
+; CHECK-NEXT: bx lr
+entry:
+ %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
+ ret <4 x i32> %out
+}
+
+define arm_aapcs_vfpcc <4 x i32> @oneoff21_i32(<4 x i32> %src1, <4 x i32> %src2) {
+; CHECK-LABEL: oneoff21_i32:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov.f32 s7, s0
+; CHECK-NEXT: vmov q0, q1
+; CHECK-NEXT: bx lr
+entry:
+ %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 4, i32 5, i32 6, i32 0>
+ ret <4 x i32> %out
+}
+
+define arm_aapcs_vfpcc <4 x i32> @oneoff22_i32(<4 x i32> %src1, <4 x i32> %src2) {
+; CHECK-LABEL: oneoff22_i32:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov q0, q1
+; CHECK-NEXT: vmov.f32 s2, s0
+; CHECK-NEXT: bx lr
+entry:
+ %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 4, i32 5, i32 4, i32 7>
+ ret <4 x i32> %out
+}
+
+define arm_aapcs_vfpcc <4 x i32> @shuffle2step_i32(<8 x i32> %src) {
+; CHECK-LABEL: shuffle2step_i32:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov.f32 s8, s1
+; CHECK-NEXT: vmov.f32 s9, s3
+; CHECK-NEXT: vmov.f32 s1, s2
+; CHECK-NEXT: vmov.f32 s10, s5
+; CHECK-NEXT: vmov.f32 s2, s4
+; CHECK-NEXT: vmov.f32 s11, s7
+; CHECK-NEXT: vmov.f32 s3, s6
+; CHECK-NEXT: vadd.i32 q0, q0, q2
+; CHECK-NEXT: bx lr
+entry:
+ %s1 = shufflevector <8 x i32> %src, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+ %s2 = shufflevector <8 x i32> %src, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+ %r = add <4 x i32> %s1, %s2
+ ret <4 x i32> %r
+}
+
+define arm_aapcs_vfpcc <4 x i32> @shuffle3step_i32(<16 x i32> %src) {
+; CHECK-LABEL: shuffle3step_i32:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .vsave {d8, d9, d10, d11}
+; CHECK-NEXT: vpush {d8, d9, d10, d11}
+; CHECK-NEXT: vmov.f32 s12, s1
+; CHECK-NEXT: vmov.f32 s13, s4
+; CHECK-NEXT: vmov r0, s10
+; CHECK-NEXT: vdup.32 q4, r0
+; CHECK-NEXT: vmov.f32 s14, s7
+; CHECK-NEXT: vmov.f32 s15, s19
+; CHECK-NEXT: vmov.f32 s16, s0
+; CHECK-NEXT: vmov.f32 s17, s3
+; CHECK-NEXT: vmov r0, s9
+; CHECK-NEXT: vmov.f32 s18, s6
+; CHECK-NEXT: vdup.32 q5, r0
+; CHECK-NEXT: vmov.f32 s4, s2
+; CHECK-NEXT: vmov.f32 s19, s23
+; CHECK-NEXT: vmov.f32 s10, s8
+; CHECK-NEXT: vadd.i32 q3, q4, q3
+; CHECK-NEXT: vmov.f32 s6, s8
+; CHECK-NEXT: vmov.f32 s7, s11
+; CHECK-NEXT: vadd.i32 q0, q3, q1
+; CHECK-NEXT: vpop {d8, d9, d10, d11}
+; CHECK-NEXT: bx lr
+entry:
+ %s1 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
+ %s2 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>
+ %s3 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11>
+ %a = add <4 x i32> %s1, %s2
+ %r = add <4 x i32> %a, %s3
+ ret <4 x i32> %r
+}
+
+define arm_aapcs_vfpcc <4 x i32> @shuffle4step_i32(<16 x i32> %src) {
+; CHECK-LABEL: shuffle4step_i32:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .vsave {d8, d9, d10, d11}
+; CHECK-NEXT: vpush {d8, d9, d10, d11}
+; CHECK-NEXT: vmov.f32 s18, s11
+; CHECK-NEXT: vmov.f32 s20, s2
+; CHECK-NEXT: vmov.f32 s19, s15
+; CHECK-NEXT: vmov.f32 s21, s6
+; CHECK-NEXT: vmov.f32 s16, s3
+; CHECK-NEXT: vmov.f32 s11, s14
+; CHECK-NEXT: vmov.f32 s22, s10
+; CHECK-NEXT: vmov.f32 s17, s7
+; CHECK-NEXT: vmov.f32 s23, s14
+; CHECK-NEXT: vadd.i32 q4, q5, q4
+; CHECK-NEXT: vmov.f32 s22, s9
+; CHECK-NEXT: vmov.f32 s23, s13
+; CHECK-NEXT: vmov.f32 s20, s1
+; CHECK-NEXT: vmov.f32 s2, s8
+; CHECK-NEXT: vmov.f32 s3, s12
+; CHECK-NEXT: vmov.f32 s21, s5
+; CHECK-NEXT: vmov.f32 s1, s4
+; CHECK-NEXT: vadd.i32 q0, q0, q5
+; CHECK-NEXT: vadd.i32 q0, q0, q4
+; CHECK-NEXT: vpop {d8, d9, d10, d11}
+; CHECK-NEXT: bx lr
+entry:
+ %s1 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
+ %s2 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13>
+ %s3 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14>
+ %s4 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15>
+ %a1 = add <4 x i32> %s1, %s2
+ %a2 = add <4 x i32> %s3, %s4
+ %r = add <4 x i32> %a1, %a2
+ ret <4 x i32> %r
+}
+
+; i16
+
define arm_aapcs_vfpcc <8 x i16> @shuffle1_i16(<8 x i16> %src) {
; CHECK-LABEL: shuffle1_i16:
; CHECK: @ %bb.0: @ %entry
@@ -126,6 +263,248 @@ entry:
ret <8 x i16> %out
}
+define arm_aapcs_vfpcc <8 x i16> @oneoff11_i16(<8 x i16> %src1, <8 x i16> %src2) {
+; CHECK-LABEL: oneoff11_i16:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov.u16 r0, q0[1]
+; CHECK-NEXT: vmov.16 q1[2], r0
+; CHECK-NEXT: vmov.u16 r0, q0[3]
+; CHECK-NEXT: vmov.16 q1[3], r0
+; CHECK-NEXT: vmov.f32 s1, s5
+; CHECK-NEXT: bx lr
+entry:
+ %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 0, i32 1, i32 1, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x i16> %out
+}
+
+define arm_aapcs_vfpcc <8 x i16> @oneoff12_i16(<8 x i16> %src1, <8 x i16> %src2) {
+; CHECK-LABEL: oneoff12_i16:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov q2, q0
+; CHECK-NEXT: vmovnb.i32 q2, q1
+; CHECK-NEXT: vmov.f32 s9, s1
+; CHECK-NEXT: vmov.f32 s10, s2
+; CHECK-NEXT: vmov.f32 s11, s3
+; CHECK-NEXT: vmov q0, q2
+; CHECK-NEXT: bx lr
+entry:
+ %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x i16> %out
+}
+
+define arm_aapcs_vfpcc <8 x i16> @oneoff21_i16(<8 x i16> %src1, <8 x i16> %src2) {
+; CHECK-LABEL: oneoff21_i16:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vins.f16 s5, s0
+; CHECK-NEXT: vmov q0, q1
+; CHECK-NEXT: bx lr
+entry:
+ %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 8, i32 9, i32 10, i32 0, i32 12, i32 13, i32 14, i32 15>
+ ret <8 x i16> %out
+}
+
+define arm_aapcs_vfpcc <8 x i16> @oneoff22_i16(<8 x i16> %src1, <8 x i16> %src2) {
+; CHECK-LABEL: oneoff22_i16:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov.u16 r0, q1[6]
+; CHECK-NEXT: vmov.16 q0[0], r0
+; CHECK-NEXT: vmov.u16 r0, q1[1]
+; CHECK-NEXT: vmov.16 q0[1], r0
+; CHECK-NEXT: vmov.f32 s1, s5
+; CHECK-NEXT: vmov.f32 s2, s6
+; CHECK-NEXT: vmov.f32 s3, s7
+; CHECK-NEXT: bx lr
+entry:
+ %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 14, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ ret <8 x i16> %out
+}
+
+define arm_aapcs_vfpcc <8 x i16> @shuffle2step_i16(<16 x i16> %src) {
+; CHECK-LABEL: shuffle2step_i16:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov.u16 r0, q0[1]
+; CHECK-NEXT: vmov.f32 s8, s0
+; CHECK-NEXT: vmov.16 q3[0], r0
+; CHECK-NEXT: vmov.u16 r0, q0[3]
+; CHECK-NEXT: vins.f16 s8, s1
+; CHECK-NEXT: vmov.16 q3[1], r0
+; CHECK-NEXT: vmov.u16 r0, q0[5]
+; CHECK-NEXT: vmov.f32 s9, s2
+; CHECK-NEXT: vmov.16 q3[2], r0
+; CHECK-NEXT: vmov.u16 r0, q0[7]
+; CHECK-NEXT: vins.f16 s9, s3
+; CHECK-NEXT: vmov.16 q3[3], r0
+; CHECK-NEXT: vmov.u16 r0, q1[1]
+; CHECK-NEXT: vmov.f32 s10, s4
+; CHECK-NEXT: vmov.16 q3[4], r0
+; CHECK-NEXT: vmov.u16 r0, q1[3]
+; CHECK-NEXT: vins.f16 s10, s5
+; CHECK-NEXT: vmov.16 q3[5], r0
+; CHECK-NEXT: vmov.u16 r0, q1[5]
+; CHECK-NEXT: vmov.f32 s11, s6
+; CHECK-NEXT: vmov.16 q3[6], r0
+; CHECK-NEXT: vmov.u16 r0, q1[7]
+; CHECK-NEXT: vins.f16 s11, s7
+; CHECK-NEXT: vmov.16 q3[7], r0
+; CHECK-NEXT: vadd.i16 q0, q2, q3
+; CHECK-NEXT: bx lr
+entry:
+ %s1 = shufflevector <16 x i16> %src, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
+ %s2 = shufflevector <16 x i16> %src, <16 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
+ %r = add <8 x i16> %s1, %s2
+ ret <8 x i16> %r
+}
+
+define arm_aapcs_vfpcc <8 x i16> @shuffle3step_i16(<32 x i16> %src) {
+; CHECK-LABEL: shuffle3step_i16:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
+; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
+; CHECK-NEXT: vmov.u16 r0, q0[0]
+; CHECK-NEXT: vmov.16 q3[0], r0
+; CHECK-NEXT: vmov.u16 r0, q0[3]
+; CHECK-NEXT: vmov.16 q3[1], r0
+; CHECK-NEXT: vmov.u16 r0, q0[6]
+; CHECK-NEXT: vmov.16 q3[2], r0
+; CHECK-NEXT: vmov.u16 r0, q1[1]
+; CHECK-NEXT: vmov.16 q3[3], r0
+; CHECK-NEXT: vmov.u16 r0, q1[4]
+; CHECK-NEXT: vmov.16 q3[4], r0
+; CHECK-NEXT: vmov.u16 r0, q2[2]
+; CHECK-NEXT: vmov.16 q4[6], r0
+; CHECK-NEXT: vmov.u16 r0, q2[5]
+; CHECK-NEXT: vmov.16 q4[7], r0
+; CHECK-NEXT: vmov.u16 r0, q1[7]
+; CHECK-NEXT: vmov.16 q3[5], r0
+; CHECK-NEXT: vmov.u16 r0, q0[2]
+; CHECK-NEXT: vmov.f32 s15, s19
+; CHECK-NEXT: vmov.16 q4[0], r0
+; CHECK-NEXT: vmov.u16 r0, q0[5]
+; CHECK-NEXT: vmov.16 q4[1], r0
+; CHECK-NEXT: vmov.u16 r0, q1[0]
+; CHECK-NEXT: vmov.16 q4[2], r0
+; CHECK-NEXT: vmov.u16 r0, q1[3]
+; CHECK-NEXT: vmov.16 q4[3], r0
+; CHECK-NEXT: vmov.u16 r0, q2[4]
+; CHECK-NEXT: vmov.16 q6[6], r0
+; CHECK-NEXT: vmov.u16 r0, q2[7]
+; CHECK-NEXT: vmov.16 q6[7], r0
+; CHECK-NEXT: vmov.f32 s18, s7
+; CHECK-NEXT: vmov.f32 s26, s8
+; CHECK-NEXT: vmov q5, q6
+; CHECK-NEXT: vmov r1, s16
+; CHECK-NEXT: vmovnb.i32 q5, q4
+; CHECK-NEXT: vmov r0, s22
+; CHECK-NEXT: vmov q5[2], q5[0], r1, r0
+; CHECK-NEXT: vmov r0, s27
+; CHECK-NEXT: vmov r1, s17
+; CHECK-NEXT: vmov q5[3], q5[1], r1, r0
+; CHECK-NEXT: vmov.u16 r0, q2[0]
+; CHECK-NEXT: vmov.16 q4[5], r0
+; CHECK-NEXT: vmov.u16 r0, q1[5]
+; CHECK-NEXT: vmovx.f16 s19, s9
+; CHECK-NEXT: vins.f16 s19, s11
+; CHECK-NEXT: vmovx.f16 s8, s0
+; CHECK-NEXT: vins.f16 s8, s2
+; CHECK-NEXT: vmovx.f16 s9, s3
+; CHECK-NEXT: vmov q0, q4
+; CHECK-NEXT: vins.f16 s9, s5
+; CHECK-NEXT: vmov.16 q2[4], r0
+; CHECK-NEXT: vmovnb.i32 q0, q2
+; CHECK-NEXT: vmov r1, s8
+; CHECK-NEXT: vmov r0, s2
+; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
+; CHECK-NEXT: vmov r0, s19
+; CHECK-NEXT: vmov r1, s9
+; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
+; CHECK-NEXT: vadd.i16 q0, q3, q0
+; CHECK-NEXT: vadd.i16 q0, q0, q5
+; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
+; CHECK-NEXT: bx lr
+entry:
+ %s1 = shufflevector <32 x i16> %src, <32 x i16> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>
+ %s2 = shufflevector <32 x i16> %src, <32 x i16> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22>
+ %s3 = shufflevector <32 x i16> %src, <32 x i16> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23>
+ %a = add <8 x i16> %s1, %s2
+ %r = add <8 x i16> %a, %s3
+ ret <8 x i16> %r
+}
+
+define arm_aapcs_vfpcc <8 x i16> @shuffle4step_i16(<32 x i16> %src) {
+; CHECK-LABEL: shuffle4step_i16:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
+; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
+; CHECK-NEXT: vmov.u16 r0, q0[3]
+; CHECK-NEXT: vmov.f32 s22, s9
+; CHECK-NEXT: vmov.16 q6[0], r0
+; CHECK-NEXT: vmov.u16 r0, q0[7]
+; CHECK-NEXT: vmov.16 q6[1], r0
+; CHECK-NEXT: vmov.u16 r0, q1[3]
+; CHECK-NEXT: vmov.16 q6[2], r0
+; CHECK-NEXT: vmov.u16 r0, q2[3]
+; CHECK-NEXT: vins.f16 s22, s11
+; CHECK-NEXT: vmov.16 q7[4], r0
+; CHECK-NEXT: vmov.u16 r0, q2[7]
+; CHECK-NEXT: vmov.f32 s23, s13
+; CHECK-NEXT: vmov.16 q7[5], r0
+; CHECK-NEXT: vmov.u16 r0, q3[3]
+; CHECK-NEXT: vins.f16 s23, s15
+; CHECK-NEXT: vmov.16 q7[6], r0
+; CHECK-NEXT: vmov.u16 r0, q3[7]
+; CHECK-NEXT: vmov.f32 s20, s1
+; CHECK-NEXT: vmov.16 q7[7], r0
+; CHECK-NEXT: vmov.u16 r0, q1[7]
+; CHECK-NEXT: vmov.16 q6[3], r0
+; CHECK-NEXT: vins.f16 s20, s3
+; CHECK-NEXT: vmov.f32 s18, s8
+; CHECK-NEXT: vmov.u16 r0, q0[1]
+; CHECK-NEXT: vmov.f32 s21, s5
+; CHECK-NEXT: vins.f16 s18, s10
+; CHECK-NEXT: vmov.f32 s26, s30
+; CHECK-NEXT: vins.f16 s21, s7
+; CHECK-NEXT: vmov.f32 s27, s31
+; CHECK-NEXT: vmov.f32 s19, s12
+; CHECK-NEXT: vadd.i16 q5, q5, q6
+; CHECK-NEXT: vmov.16 q6[0], r0
+; CHECK-NEXT: vmov.u16 r0, q0[5]
+; CHECK-NEXT: vins.f16 s19, s14
+; CHECK-NEXT: vmov.16 q6[1], r0
+; CHECK-NEXT: vmov.u16 r0, q1[1]
+; CHECK-NEXT: vmov.f32 s16, s0
+; CHECK-NEXT: vmov.16 q6[2], r0
+; CHECK-NEXT: vmov.u16 r0, q2[1]
+; CHECK-NEXT: vins.f16 s16, s2
+; CHECK-NEXT: vmov.16 q0[4], r0
+; CHECK-NEXT: vmov.u16 r0, q2[5]
+; CHECK-NEXT: vmov.f32 s17, s4
+; CHECK-NEXT: vmov.16 q0[5], r0
+; CHECK-NEXT: vmov.u16 r0, q3[1]
+; CHECK-NEXT: vmov.16 q0[6], r0
+; CHECK-NEXT: vmov.u16 r0, q3[5]
+; CHECK-NEXT: vmov.16 q0[7], r0
+; CHECK-NEXT: vmov.u16 r0, q1[5]
+; CHECK-NEXT: vmov.16 q6[3], r0
+; CHECK-NEXT: vins.f16 s17, s6
+; CHECK-NEXT: vmov.f32 s26, s2
+; CHECK-NEXT: vmov.f32 s27, s3
+; CHECK-NEXT: vadd.i16 q0, q4, q6
+; CHECK-NEXT: vadd.i16 q0, q0, q5
+; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
+; CHECK-NEXT: bx lr
+entry:
+ %s1 = shufflevector <32 x i16> %src, <32 x i16> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>
+ %s2 = shufflevector <32 x i16> %src, <32 x i16> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29>
+ %s3 = shufflevector <32 x i16> %src, <32 x i16> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30>
+ %s4 = shufflevector <32 x i16> %src, <32 x i16> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31>
+ %a1 = add <8 x i16> %s1, %s2
+ %a2 = add <8 x i16> %s3, %s4
+ %r = add <8 x i16> %a1, %a2
+ ret <8 x i16> %r
+}
+
+; i8
+
define arm_aapcs_vfpcc <16 x i8> @shuffle1_i8(<16 x i8> %src) {
; CHECK-LABEL: shuffle1_i8:
; CHECK: @ %bb.0: @ %entry
@@ -250,6 +629,454 @@ entry:
ret <16 x i8> %out
}
+define arm_aapcs_vfpcc <16 x i8> @oneoff11_i8(<16 x i8> %src1, <16 x i8> %src2) {
+; CHECK-LABEL: oneoff11_i8:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov.u8 r0, q0[0]
+; CHECK-NEXT: vmov.8 q1[0], r0
+; CHECK-NEXT: vmov.u8 r0, q0[1]
+; CHECK-NEXT: vmov.8 q1[1], r0
+; CHECK-NEXT: vmov.8 q1[2], r0
+; CHECK-NEXT: vmov.u8 r0, q0[3]
+; CHECK-NEXT: vmov.8 q1[3], r0
+; CHECK-NEXT: vmov.f32 s5, s1
+; CHECK-NEXT: vmov.f32 s6, s2
+; CHECK-NEXT: vmov.f32 s7, s3
+; CHECK-NEXT: vmov q0, q1
+; CHECK-NEXT: bx lr
+entry:
+ %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 0, i32 1, i32 1, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ ret <16 x i8> %out
+}
+
+define arm_aapcs_vfpcc <16 x i8> @oneoff12_i8(<16 x i8> %src1, <16 x i8> %src2) {
+; CHECK-LABEL: oneoff12_i8:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov.u8 r0, q1[4]
+; CHECK-NEXT: vmov.8 q1[0], r0
+; CHECK-NEXT: vmov.u8 r0, q0[1]
+; CHECK-NEXT: vmov.8 q1[1], r0
+; CHECK-NEXT: vmov.u8 r0, q0[2]
+; CHECK-NEXT: vmov.8 q1[2], r0
+; CHECK-NEXT: vmov.u8 r0, q0[3]
+; CHECK-NEXT: vmov.8 q1[3], r0
+; CHECK-NEXT: vmov.f32 s5, s1
+; CHECK-NEXT: vmov.f32 s6, s2
+; CHECK-NEXT: vmov.f32 s7, s3
+; CHECK-NEXT: vmov q0, q1
+; CHECK-NEXT: bx lr
+entry:
+ %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 20, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ ret <16 x i8> %out
+}
+
+define arm_aapcs_vfpcc <16 x i8> @oneoff21_i8(<16 x i8> %src1, <16 x i8> %src2) {
+; CHECK-LABEL: oneoff21_i8:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov.u8 r0, q1[0]
+; CHECK-NEXT: vmov q2, q0
+; CHECK-NEXT: vmov.8 q0[0], r0
+; CHECK-NEXT: vmov.u8 r0, q1[1]
+; CHECK-NEXT: vmov.8 q0[1], r0
+; CHECK-NEXT: vmov.u8 r0, q1[2]
+; CHECK-NEXT: vmov.8 q0[2], r0
+; CHECK-NEXT: vmov.u8 r0, q2[0]
+; CHECK-NEXT: vmov.8 q0[3], r0
+; CHECK-NEXT: vmov.f32 s1, s5
+; CHECK-NEXT: vmov.f32 s2, s6
+; CHECK-NEXT: vmov.f32 s3, s7
+; CHECK-NEXT: bx lr
+entry:
+ %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 16, i32 17, i32 18, i32 0, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+ ret <16 x i8> %out
+}
+
+define arm_aapcs_vfpcc <16 x i8> @oneoff22_i8(<16 x i8> %src1, <16 x i8> %src2) {
+; CHECK-LABEL: oneoff22_i8:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov q0, q1
+; CHECK-NEXT: vmov.u8 r0, q1[8]
+; CHECK-NEXT: vmov.8 q1[8], r0
+; CHECK-NEXT: vmov.u8 r0, q0[15]
+; CHECK-NEXT: vmov.8 q1[9], r0
+; CHECK-NEXT: vmov.u8 r0, q0[10]
+; CHECK-NEXT: vmov.8 q1[10], r0
+; CHECK-NEXT: vmov.u8 r0, q0[11]
+; CHECK-NEXT: vmov.8 q1[11], r0
+; CHECK-NEXT: vmov.f32 s2, s6
+; CHECK-NEXT: bx lr
+entry:
+ %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 31, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+ ret <16 x i8> %out
+}
+
+define arm_aapcs_vfpcc <16 x i8> @shuffle2step_i8(<32 x i8> %src) {
+; CHECK-LABEL: shuffle2step_i8:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov.u8 r0, q0[0]
+; CHECK-NEXT: vmov.8 q2[0], r0
+; CHECK-NEXT: vmov.u8 r0, q0[2]
+; CHECK-NEXT: vmov.8 q2[1], r0
+; CHECK-NEXT: vmov.u8 r0, q0[4]
+; CHECK-NEXT: vmov.8 q2[2], r0
+; CHECK-NEXT: vmov.u8 r0, q0[6]
+; CHECK-NEXT: vmov.8 q2[3], r0
+; CHECK-NEXT: vmov.u8 r0, q0[8]
+; CHECK-NEXT: vmov.8 q2[4], r0
+; CHECK-NEXT: vmov.u8 r0, q0[10]
+; CHECK-NEXT: vmov.8 q2[5], r0
+; CHECK-NEXT: vmov.u8 r0, q0[12]
+; CHECK-NEXT: vmov.8 q2[6], r0
+; CHECK-NEXT: vmov.u8 r0, q0[14]
+; CHECK-NEXT: vmov.8 q2[7], r0
+; CHECK-NEXT: vmov.u8 r0, q1[0]
+; CHECK-NEXT: vmov.8 q2[8], r0
+; CHECK-NEXT: vmov.u8 r0, q1[2]
+; CHECK-NEXT: vmov.8 q2[9], r0
+; CHECK-NEXT: vmov.u8 r0, q1[4]
+; CHECK-NEXT: vmov.8 q2[10], r0
+; CHECK-NEXT: vmov.u8 r0, q1[6]
+; CHECK-NEXT: vmov.8 q2[11], r0
+; CHECK-NEXT: vmov.u8 r0, q1[8]
+; CHECK-NEXT: vmov.8 q2[12], r0
+; CHECK-NEXT: vmov.u8 r0, q1[10]
+; CHECK-NEXT: vmov.8 q2[13], r0
+; CHECK-NEXT: vmov.u8 r0, q1[12]
+; CHECK-NEXT: vmov.8 q2[14], r0
+; CHECK-NEXT: vmov.u8 r0, q0[1]
+; CHECK-NEXT: vmov.8 q3[0], r0
+; CHECK-NEXT: vmov.u8 r0, q0[3]
+; CHECK-NEXT: vmov.8 q3[1], r0
+; CHECK-NEXT: vmov.u8 r0, q0[5]
+; CHECK-NEXT: vmov.8 q3[2], r0
+; CHECK-NEXT: vmov.u8 r0, q0[7]
+; CHECK-NEXT: vmov.8 q3[3], r0
+; CHECK-NEXT: vmov.u8 r0, q0[9]
+; CHECK-NEXT: vmov.8 q3[4], r0
+; CHECK-NEXT: vmov.u8 r0, q0[11]
+; CHECK-NEXT: vmov.8 q3[5], r0
+; CHECK-NEXT: vmov.u8 r0, q0[13]
+; CHECK-NEXT: vmov.8 q3[6], r0
+; CHECK-NEXT: vmov.u8 r0, q0[15]
+; CHECK-NEXT: vmov.8 q3[7], r0
+; CHECK-NEXT: vmov.u8 r0, q1[1]
+; CHECK-NEXT: vmov.8 q3[8], r0
+; CHECK-NEXT: vmov.u8 r0, q1[3]
+; CHECK-NEXT: vmov.8 q3[9], r0
+; CHECK-NEXT: vmov.u8 r0, q1[5]
+; CHECK-NEXT: vmov.8 q3[10], r0
+; CHECK-NEXT: vmov.u8 r0, q1[7]
+; CHECK-NEXT: vmov.8 q3[11], r0
+; CHECK-NEXT: vmov.u8 r0, q1[9]
+; CHECK-NEXT: vmov.8 q3[12], r0
+; CHECK-NEXT: vmov.u8 r0, q1[11]
+; CHECK-NEXT: vmov.8 q3[13], r0
+; CHECK-NEXT: vmov.u8 r0, q1[13]
+; CHECK-NEXT: vmov.8 q3[14], r0
+; CHECK-NEXT: vmov.u8 r0, q1[15]
+; CHECK-NEXT: vmov.8 q3[15], r0
+; CHECK-NEXT: vmov.u8 r0, q1[14]
+; CHECK-NEXT: vmov.8 q2[15], r0
+; CHECK-NEXT: vadd.i8 q0, q2, q3
+; CHECK-NEXT: bx lr
+entry:
+ %s1 = shufflevector <32 x i8> %src, <32 x i8> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
+ %s2 = shufflevector <32 x i8> %src, <32 x i8> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
+ %r = add <16 x i8> %s1, %s2
+ ret <16 x i8> %r
+}
+
+define arm_aapcs_vfpcc <16 x i8> @shuffle3step_i8(<64 x i8> %src) {
+; CHECK-LABEL: shuffle3step_i8:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
+; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
+; CHECK-NEXT: vmov.u8 r1, q0[1]
+; CHECK-NEXT: vmov.u8 r0, q1[9]
+; CHECK-NEXT: vmov.8 q4[0], r1
+; CHECK-NEXT: vmov.u8 r1, q0[4]
+; CHECK-NEXT: vmov.8 q4[1], r1
+; CHECK-NEXT: vmov.u8 r1, q0[7]
+; CHECK-NEXT: vmov.8 q4[2], r1
+; CHECK-NEXT: vmov.u8 r1, q0[10]
+; CHECK-NEXT: vmov.8 q4[3], r1
+; CHECK-NEXT: vmov.u8 r1, q0[13]
+; CHECK-NEXT: vmov.8 q3[8], r0
+; CHECK-NEXT: vmov.u8 r0, q1[12]
+; CHECK-NEXT: vmov.8 q4[4], r1
+; CHECK-NEXT: vmov.u8 r1, q1[0]
+; CHECK-NEXT: vmov.8 q3[9], r0
+; CHECK-NEXT: vmov.u8 r0, q1[15]
+; CHECK-NEXT: vmov.8 q4[5], r1
+; CHECK-NEXT: vmov.u8 r1, q1[3]
+; CHECK-NEXT: vmov.8 q3[10], r0
+; CHECK-NEXT: vmov.u8 r0, q2[2]
+; CHECK-NEXT: vmov.8 q4[6], r1
+; CHECK-NEXT: vmov.u8 r1, q1[6]
+; CHECK-NEXT: vmov.8 q3[11], r0
+; CHECK-NEXT: vmov.8 q4[7], r1
+; CHECK-NEXT: vmov r0, s14
+; CHECK-NEXT: vmov r1, s16
+; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
+; CHECK-NEXT: vmov.u8 r0, q2[5]
+; CHECK-NEXT: vmov.8 q5[12], r0
+; CHECK-NEXT: vmov.u8 r0, q2[8]
+; CHECK-NEXT: vmov.8 q5[13], r0
+; CHECK-NEXT: vmov.u8 r0, q2[11]
+; CHECK-NEXT: vmov.8 q5[14], r0
+; CHECK-NEXT: vmov.u8 r0, q2[14]
+; CHECK-NEXT: vmov.8 q5[15], r0
+; CHECK-NEXT: vmov r1, s17
+; CHECK-NEXT: vmov r0, s23
+; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
+; CHECK-NEXT: vmov.u8 r0, q1[8]
+; CHECK-NEXT: vmov.8 q4[8], r0
+; CHECK-NEXT: vmov.u8 r0, q1[11]
+; CHECK-NEXT: vmov.8 q4[9], r0
+; CHECK-NEXT: vmov.u8 r0, q1[14]
+; CHECK-NEXT: vmov.8 q4[10], r0
+; CHECK-NEXT: vmov.u8 r0, q2[1]
+; CHECK-NEXT: vmov.8 q4[11], r0
+; CHECK-NEXT: vmov.u8 r1, q0[0]
+; CHECK-NEXT: vmov r0, s18
+; CHECK-NEXT: vmov.8 q4[0], r1
+; CHECK-NEXT: vmov.u8 r1, q0[3]
+; CHECK-NEXT: vmov.8 q4[1], r1
+; CHECK-NEXT: vmov.u8 r1, q0[6]
+; CHECK-NEXT: vmov.8 q4[2], r1
+; CHECK-NEXT: vmov.u8 r1, q0[9]
+; CHECK-NEXT: vmov.8 q4[3], r1
+; CHECK-NEXT: vmov.u8 r1, q0[12]
+; CHECK-NEXT: vmov.8 q4[4], r1
+; CHECK-NEXT: vmov.u8 r1, q0[15]
+; CHECK-NEXT: vmov.8 q4[5], r1
+; CHECK-NEXT: vmov.u8 r1, q1[2]
+; CHECK-NEXT: vmov.8 q4[6], r1
+; CHECK-NEXT: vmov.u8 r1, q1[5]
+; CHECK-NEXT: vmov.8 q4[7], r1
+; CHECK-NEXT: vmov r1, s16
+; CHECK-NEXT: vmov q5[2], q5[0], r1, r0
+; CHECK-NEXT: vmov.u8 r0, q2[4]
+; CHECK-NEXT: vmov.8 q6[12], r0
+; CHECK-NEXT: vmov.u8 r0, q2[7]
+; CHECK-NEXT: vmov.8 q6[13], r0
+; CHECK-NEXT: vmov.u8 r0, q2[10]
+; CHECK-NEXT: vmov.8 q6[14], r0
+; CHECK-NEXT: vmov.u8 r0, q2[13]
+; CHECK-NEXT: vmov.8 q6[15], r0
+; CHECK-NEXT: vmov r1, s17
+; CHECK-NEXT: vmov r0, s27
+; CHECK-NEXT: vmov q5[3], q5[1], r1, r0
+; CHECK-NEXT: vmov.u8 r0, q0[2]
+; CHECK-NEXT: vmov.8 q4[0], r0
+; CHECK-NEXT: vmov.u8 r0, q0[5]
+; CHECK-NEXT: vmov.8 q4[1], r0
+; CHECK-NEXT: vmov.u8 r0, q0[8]
+; CHECK-NEXT: vmov.8 q4[2], r0
+; CHECK-NEXT: vmov.u8 r0, q0[11]
+; CHECK-NEXT: vmov.8 q4[3], r0
+; CHECK-NEXT: vmov.u8 r0, q0[14]
+; CHECK-NEXT: vmov.8 q4[4], r0
+; CHECK-NEXT: vmov.u8 r0, q1[1]
+; CHECK-NEXT: vmov.8 q4[5], r0
+; CHECK-NEXT: vmov.u8 r0, q1[4]
+; CHECK-NEXT: vmov.8 q4[6], r0
+; CHECK-NEXT: vmov.u8 r0, q1[10]
+; CHECK-NEXT: vmov.8 q0[8], r0
+; CHECK-NEXT: vmov.u8 r0, q1[13]
+; CHECK-NEXT: vmov.8 q0[9], r0
+; CHECK-NEXT: vmov.u8 r0, q2[0]
+; CHECK-NEXT: vmov.8 q0[10], r0
+; CHECK-NEXT: vmov.u8 r0, q2[3]
+; CHECK-NEXT: vmov.8 q0[11], r0
+; CHECK-NEXT: vmov.u8 r0, q1[7]
+; CHECK-NEXT: vmov.8 q4[7], r0
+; CHECK-NEXT: vmov r0, s2
+; CHECK-NEXT: vmov r1, s16
+; CHECK-NEXT: vadd.i8 q3, q5, q3
+; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
+; CHECK-NEXT: vmov.u8 r0, q2[6]
+; CHECK-NEXT: vmov.8 q1[12], r0
+; CHECK-NEXT: vmov.u8 r0, q2[9]
+; CHECK-NEXT: vmov.8 q1[13], r0
+; CHECK-NEXT: vmov.u8 r0, q2[12]
+; CHECK-NEXT: vmov.8 q1[14], r0
+; CHECK-NEXT: vmov.u8 r0, q2[15]
+; CHECK-NEXT: vmov.8 q1[15], r0
+; CHECK-NEXT: vmov r1, s17
+; CHECK-NEXT: vmov r0, s7
+; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
+; CHECK-NEXT: vadd.i8 q0, q3, q0
+; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
+; CHECK-NEXT: bx lr
+entry:
+ %s1 = shufflevector <64 x i8> %src, <64 x i8> undef, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45>
+ %s2 = shufflevector <64 x i8> %src, <64 x i8> undef, <16 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22, i32 25, i32 28, i32 31, i32 34, i32 37, i32 40, i32 43, i32 46>
+ %s3 = shufflevector <64 x i8> %src, <64 x i8> undef, <16 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23, i32 26, i32 29, i32 32, i32 35, i32 38, i32 41, i32 44, i32 47>
+ %a = add <16 x i8> %s1, %s2
+ %r = add <16 x i8> %a, %s3
+ ret <16 x i8> %r
+}
+
+define arm_aapcs_vfpcc <16 x i8> @shuffle4step_i8(<64 x i8> %src) {
+; CHECK-LABEL: shuffle4step_i8:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
+; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
+; CHECK-NEXT: vmov.u8 r0, q0[3]
+; CHECK-NEXT: vmov.8 q4[0], r0
+; CHECK-NEXT: vmov.u8 r0, q0[7]
+; CHECK-NEXT: vmov.8 q4[1], r0
+; CHECK-NEXT: vmov.u8 r0, q0[11]
+; CHECK-NEXT: vmov.8 q4[2], r0
+; CHECK-NEXT: vmov.u8 r0, q0[15]
+; CHECK-NEXT: vmov.8 q4[3], r0
+; CHECK-NEXT: vmov.u8 r0, q1[3]
+; CHECK-NEXT: vmov.8 q4[4], r0
+; CHECK-NEXT: vmov.u8 r0, q1[7]
+; CHECK-NEXT: vmov.8 q4[5], r0
+; CHECK-NEXT: vmov.u8 r0, q1[11]
+; CHECK-NEXT: vmov.8 q4[6], r0
+; CHECK-NEXT: vmov.u8 r0, q2[3]
+; CHECK-NEXT: vmov.8 q5[8], r0
+; CHECK-NEXT: vmov.u8 r0, q2[7]
+; CHECK-NEXT: vmov.8 q5[9], r0
+; CHECK-NEXT: vmov.u8 r0, q2[11]
+; CHECK-NEXT: vmov.8 q5[10], r0
+; CHECK-NEXT: vmov.u8 r0, q2[15]
+; CHECK-NEXT: vmov.8 q5[11], r0
+; CHECK-NEXT: vmov.u8 r0, q3[3]
+; CHECK-NEXT: vmov.8 q5[12], r0
+; CHECK-NEXT: vmov.u8 r0, q3[7]
+; CHECK-NEXT: vmov.8 q5[13], r0
+; CHECK-NEXT: vmov.u8 r0, q3[11]
+; CHECK-NEXT: vmov.8 q5[14], r0
+; CHECK-NEXT: vmov.u8 r0, q3[15]
+; CHECK-NEXT: vmov.8 q5[15], r0
+; CHECK-NEXT: vmov.u8 r0, q1[15]
+; CHECK-NEXT: vmov.8 q4[7], r0
+; CHECK-NEXT: vmov.u8 r0, q0[2]
+; CHECK-NEXT: vmov.f32 s18, s22
+; CHECK-NEXT: vmov.f32 s19, s23
+; CHECK-NEXT: vmov.8 q5[0], r0
+; CHECK-NEXT: vmov.u8 r0, q0[6]
+; CHECK-NEXT: vmov.8 q5[1], r0
+; CHECK-NEXT: vmov.u8 r0, q0[10]
+; CHECK-NEXT: vmov.8 q5[2], r0
+; CHECK-NEXT: vmov.u8 r0, q0[14]
+; CHECK-NEXT: vmov.8 q5[3], r0
+; CHECK-NEXT: vmov.u8 r0, q1[2]
+; CHECK-NEXT: vmov.8 q5[4], r0
+; CHECK-NEXT: vmov.u8 r0, q1[6]
+; CHECK-NEXT: vmov.8 q5[5], r0
+; CHECK-NEXT: vmov.u8 r0, q1[10]
+; CHECK-NEXT: vmov.8 q5[6], r0
+; CHECK-NEXT: vmov.u8 r0, q2[2]
+; CHECK-NEXT: vmov.8 q6[8], r0
+; CHECK-NEXT: vmov.u8 r0, q2[6]
+; CHECK-NEXT: vmov.8 q6[9], r0
+; CHECK-NEXT: vmov.u8 r0, q2[10]
+; CHECK-NEXT: vmov.8 q6[10], r0
+; CHECK-NEXT: vmov.u8 r0, q2[14]
+; CHECK-NEXT: vmov.8 q6[11], r0
+; CHECK-NEXT: vmov.u8 r0, q3[2]
+; CHECK-NEXT: vmov.8 q6[12], r0
+; CHECK-NEXT: vmov.u8 r0, q3[6]
+; CHECK-NEXT: vmov.8 q6[13], r0
+; CHECK-NEXT: vmov.u8 r0, q3[10]
+; CHECK-NEXT: vmov.8 q6[14], r0
+; CHECK-NEXT: vmov.u8 r0, q3[14]
+; CHECK-NEXT: vmov.8 q6[15], r0
+; CHECK-NEXT: vmov.u8 r0, q1[14]
+; CHECK-NEXT: vmov.8 q5[7], r0
+; CHECK-NEXT: vmov.u8 r0, q0[1]
+; CHECK-NEXT: vmov.f32 s22, s26
+; CHECK-NEXT: vmov.f32 s23, s27
+; CHECK-NEXT: vadd.i8 q4, q5, q4
+; CHECK-NEXT: vmov.8 q5[0], r0
+; CHECK-NEXT: vmov.u8 r0, q0[5]
+; CHECK-NEXT: vmov.8 q5[1], r0
+; CHECK-NEXT: vmov.u8 r0, q0[9]
+; CHECK-NEXT: vmov.8 q5[2], r0
+; CHECK-NEXT: vmov.u8 r0, q0[13]
+; CHECK-NEXT: vmov.8 q5[3], r0
+; CHECK-NEXT: vmov.u8 r0, q1[1]
+; CHECK-NEXT: vmov.8 q5[4], r0
+; CHECK-NEXT: vmov.u8 r0, q1[5]
+; CHECK-NEXT: vmov.8 q5[5], r0
+; CHECK-NEXT: vmov.u8 r0, q1[9]
+; CHECK-NEXT: vmov.8 q5[6], r0
+; CHECK-NEXT: vmov.u8 r0, q2[1]
+; CHECK-NEXT: vmov.8 q6[8], r0
+; CHECK-NEXT: vmov.u8 r0, q2[5]
+; CHECK-NEXT: vmov.8 q6[9], r0
+; CHECK-NEXT: vmov.u8 r0, q2[9]
+; CHECK-NEXT: vmov.8 q6[10], r0
+; CHECK-NEXT: vmov.u8 r0, q2[13]
+; CHECK-NEXT: vmov.8 q6[11], r0
+; CHECK-NEXT: vmov.u8 r0, q3[1]
+; CHECK-NEXT: vmov.8 q6[12], r0
+; CHECK-NEXT: vmov.u8 r0, q3[5]
+; CHECK-NEXT: vmov.8 q6[13], r0
+; CHECK-NEXT: vmov.u8 r0, q3[9]
+; CHECK-NEXT: vmov.8 q6[14], r0
+; CHECK-NEXT: vmov.u8 r0, q3[13]
+; CHECK-NEXT: vmov.8 q6[15], r0
+; CHECK-NEXT: vmov.u8 r0, q1[13]
+; CHECK-NEXT: vmov.8 q5[7], r0
+; CHECK-NEXT: vmov.u8 r0, q0[0]
+; CHECK-NEXT: vmov.f32 s22, s26
+; CHECK-NEXT: vmov.f32 s23, s27
+; CHECK-NEXT: vmov.8 q6[0], r0
+; CHECK-NEXT: vmov.u8 r0, q0[4]
+; CHECK-NEXT: vmov.8 q6[1], r0
+; CHECK-NEXT: vmov.u8 r0, q0[8]
+; CHECK-NEXT: vmov.8 q6[2], r0
+; CHECK-NEXT: vmov.u8 r0, q0[12]
+; CHECK-NEXT: vmov.8 q6[3], r0
+; CHECK-NEXT: vmov.u8 r0, q1[0]
+; CHECK-NEXT: vmov.8 q6[4], r0
+; CHECK-NEXT: vmov.u8 r0, q1[4]
+; CHECK-NEXT: vmov.8 q6[5], r0
+; CHECK-NEXT: vmov.u8 r0, q1[8]
+; CHECK-NEXT: vmov.8 q6[6], r0
+; CHECK-NEXT: vmov.u8 r0, q2[0]
+; CHECK-NEXT: vmov.8 q0[8], r0
+; CHECK-NEXT: vmov.u8 r0, q2[4]
+; CHECK-NEXT: vmov.8 q0[9], r0
+; CHECK-NEXT: vmov.u8 r0, q2[8]
+; CHECK-NEXT: vmov.8 q0[10], r0
+; CHECK-NEXT: vmov.u8 r0, q2[12]
+; CHECK-NEXT: vmov.8 q0[11], r0
+; CHECK-NEXT: vmov.u8 r0, q3[0]
+; CHECK-NEXT: vmov.8 q0[12], r0
+; CHECK-NEXT: vmov.u8 r0, q3[4]
+; CHECK-NEXT: vmov.8 q0[13], r0
+; CHECK-NEXT: vmov.u8 r0, q3[8]
+; CHECK-NEXT: vmov.8 q0[14], r0
+; CHECK-NEXT: vmov.u8 r0, q3[12]
+; CHECK-NEXT: vmov.8 q0[15], r0
+; CHECK-NEXT: vmov.u8 r0, q1[12]
+; CHECK-NEXT: vmov.8 q6[7], r0
+; CHECK-NEXT: vmov.f32 s26, s2
+; CHECK-NEXT: vmov.f32 s27, s3
+; CHECK-NEXT: vadd.i8 q0, q6, q5
+; CHECK-NEXT: vadd.i8 q0, q0, q4
+; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
+; CHECK-NEXT: bx lr
+entry:
+ %s1 = shufflevector <64 x i8> %src, <64 x i8> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 32, i32 36, i32 40, i32 44, i32 48, i32 52, i32 56, i32 60>
+ %s2 = shufflevector <64 x i8> %src, <64 x i8> undef, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 61>
+ %s3 = shufflevector <64 x i8> %src, <64 x i8> undef, <16 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30, i32 34, i32 38, i32 42, i32 46, i32 50, i32 54, i32 58, i32 62>
+ %s4 = shufflevector <64 x i8> %src, <64 x i8> undef, <16 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31, i32 35, i32 39, i32 43, i32 47, i32 51, i32 55, i32 59, i32 63>
+ %a1 = add <16 x i8> %s1, %s2
+ %a2 = add <16 x i8> %s3, %s4
+ %r = add <16 x i8> %a1, %a2
+ ret <16 x i8> %r
+}
+
+; i64
+
define arm_aapcs_vfpcc <2 x i64> @shuffle1_i64(<2 x i64> %src) {
; CHECK-LABEL: shuffle1_i64:
; CHECK: @ %bb.0: @ %entry
@@ -282,6 +1109,8 @@ entry:
ret <2 x i64> %out
}
+; f32
+
define arm_aapcs_vfpcc <4 x float> @shuffle1_f32(<4 x float> %src) {
; CHECK-LABEL: shuffle1_f32:
; CHECK: @ %bb.0: @ %entry
@@ -330,6 +1159,139 @@ entry:
ret <4 x float> %out
}
+define arm_aapcs_vfpcc <4 x float> @oneoff11_f32(<4 x float> %src1, <4 x float> %src2) {
+; CHECK-LABEL: oneoff11_f32:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov.f32 s2, s1
+; CHECK-NEXT: bx lr
+entry:
+ %out = shufflevector <4 x float> %src1, <4 x float> %src2, <4 x i32> <i32 0, i32 1, i32 1, i32 3>
+ ret <4 x float> %out
+}
+
+define arm_aapcs_vfpcc <4 x float> @oneoff12_f32(<4 x float> %src1, <4 x float> %src2) {
+; CHECK-LABEL: oneoff12_f32:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov.f32 s5, s1
+; CHECK-NEXT: vmov.f32 s6, s2
+; CHECK-NEXT: vmov.f32 s7, s3
+; CHECK-NEXT: vmov q0, q1
+; CHECK-NEXT: bx lr
+entry:
+ %out = shufflevector <4 x float> %src1, <4 x float> %src2, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
+ ret <4 x float> %out
+}
+
+define arm_aapcs_vfpcc <4 x float> @oneoff21_f32(<4 x float> %src1, <4 x float> %src2) {
+; CHECK-LABEL: oneoff21_f32:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov.f32 s7, s0
+; CHECK-NEXT: vmov q0, q1
+; CHECK-NEXT: bx lr
+entry:
+ %out = shufflevector <4 x float> %src1, <4 x float> %src2, <4 x i32> <i32 4, i32 5, i32 6, i32 0>
+ ret <4 x float> %out
+}
+
+define arm_aapcs_vfpcc <4 x float> @oneoff22_f32(<4 x float> %src1, <4 x float> %src2) {
+; CHECK-LABEL: oneoff22_f32:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov q0, q1
+; CHECK-NEXT: vmov.f32 s2, s0
+; CHECK-NEXT: bx lr
+entry:
+ %out = shufflevector <4 x float> %src1, <4 x float> %src2, <4 x i32> <i32 4, i32 5, i32 4, i32 7>
+ ret <4 x float> %out
+}
+
+define arm_aapcs_vfpcc <4 x float> @shuffle2step_f32(<8 x float> %src) {
+; CHECKFP-LABEL: shuffle2step_f32:
+; CHECKFP: @ %bb.0: @ %entry
+; CHECKFP-NEXT: vmov.f32 s8, s1
+; CHECKFP-NEXT: vmov.f32 s9, s3
+; CHECKFP-NEXT: vmov.f32 s1, s2
+; CHECKFP-NEXT: vmov.f32 s10, s5
+; CHECKFP-NEXT: vmov.f32 s2, s4
+; CHECKFP-NEXT: vmov.f32 s11, s7
+; CHECKFP-NEXT: vmov.f32 s3, s6
+; CHECKFP-NEXT: vadd.f32 q0, q0, q2
+; CHECKFP-NEXT: bx lr
+entry:
+ %s1 = shufflevector <8 x float> %src, <8 x float> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+ %s2 = shufflevector <8 x float> %src, <8 x float> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+ %r = fadd <4 x float> %s1, %s2
+ ret <4 x float> %r
+}
+
+define arm_aapcs_vfpcc <4 x float> @shuffle3step_f32(<16 x float> %src) {
+; CHECKFP-LABEL: shuffle3step_f32:
+; CHECKFP: @ %bb.0: @ %entry
+; CHECKFP-NEXT: .vsave {d8, d9}
+; CHECKFP-NEXT: vpush {d8, d9}
+; CHECKFP-NEXT: vmov.f32 s12, s1
+; CHECKFP-NEXT: vmov.f32 s16, s0
+; CHECKFP-NEXT: vmov.f32 s13, s4
+; CHECKFP-NEXT: vmov.f32 s17, s3
+; CHECKFP-NEXT: vmov.f32 s14, s7
+; CHECKFP-NEXT: vmov.f32 s18, s6
+; CHECKFP-NEXT: vmov.f32 s4, s2
+; CHECKFP-NEXT: vmov.f32 s15, s10
+; CHECKFP-NEXT: vmov.f32 s19, s9
+; CHECKFP-NEXT: vmov.f32 s10, s8
+; CHECKFP-NEXT: vadd.f32 q3, q4, q3
+; CHECKFP-NEXT: vmov.f32 s6, s8
+; CHECKFP-NEXT: vmov.f32 s7, s11
+; CHECKFP-NEXT: vadd.f32 q0, q3, q1
+; CHECKFP-NEXT: vpop {d8, d9}
+; CHECKFP-NEXT: bx lr
+entry:
+ %s1 = shufflevector <16 x float> %src, <16 x float> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
+ %s2 = shufflevector <16 x float> %src, <16 x float> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>
+ %s3 = shufflevector <16 x float> %src, <16 x float> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11>
+ %a = fadd <4 x float> %s1, %s2
+ %r = fadd <4 x float> %a, %s3
+ ret <4 x float> %r
+}
+
+define arm_aapcs_vfpcc <4 x float> @shuffle4step_f32(<16 x float> %src) {
+; CHECKFP-LABEL: shuffle4step_f32:
+; CHECKFP: @ %bb.0: @ %entry
+; CHECKFP-NEXT: .vsave {d8, d9, d10, d11}
+; CHECKFP-NEXT: vpush {d8, d9, d10, d11}
+; CHECKFP-NEXT: vmov.f32 s18, s11
+; CHECKFP-NEXT: vmov.f32 s20, s2
+; CHECKFP-NEXT: vmov.f32 s19, s15
+; CHECKFP-NEXT: vmov.f32 s21, s6
+; CHECKFP-NEXT: vmov.f32 s16, s3
+; CHECKFP-NEXT: vmov.f32 s11, s14
+; CHECKFP-NEXT: vmov.f32 s22, s10
+; CHECKFP-NEXT: vmov.f32 s17, s7
+; CHECKFP-NEXT: vmov.f32 s23, s14
+; CHECKFP-NEXT: vadd.f32 q4, q5, q4
+; CHECKFP-NEXT: vmov.f32 s22, s9
+; CHECKFP-NEXT: vmov.f32 s23, s13
+; CHECKFP-NEXT: vmov.f32 s20, s1
+; CHECKFP-NEXT: vmov.f32 s2, s8
+; CHECKFP-NEXT: vmov.f32 s3, s12
+; CHECKFP-NEXT: vmov.f32 s21, s5
+; CHECKFP-NEXT: vmov.f32 s1, s4
+; CHECKFP-NEXT: vadd.f32 q0, q0, q5
+; CHECKFP-NEXT: vadd.f32 q0, q0, q4
+; CHECKFP-NEXT: vpop {d8, d9, d10, d11}
+; CHECKFP-NEXT: bx lr
+entry:
+ %s1 = shufflevector <16 x float> %src, <16 x float> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
+ %s2 = shufflevector <16 x float> %src, <16 x float> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13>
+ %s3 = shufflevector <16 x float> %src, <16 x float> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14>
+ %s4 = shufflevector <16 x float> %src, <16 x float> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15>
+ %a1 = fadd <4 x float> %s1, %s2
+ %a2 = fadd <4 x float> %s3, %s4
+ %r = fadd <4 x float> %a1, %a2
+ ret <4 x float> %r
+}
+
+; f16
+
define arm_aapcs_vfpcc <8 x half> @shuffle1_f16(<8 x half> %src) {
; CHECK-LABEL: shuffle1_f16:
; CHECK: @ %bb.0: @ %entry
@@ -396,6 +1358,221 @@ entry:
ret <8 x half> %out
}
+define arm_aapcs_vfpcc <8 x half> @oneoff11_f16(<8 x half> %src1, <8 x half> %src2) {
+; CHECK-LABEL: oneoff11_f16:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmovx.f16 s4, s1
+; CHECK-NEXT: vmovx.f16 s1, s0
+; CHECK-NEXT: vins.f16 s1, s4
+; CHECK-NEXT: bx lr
+entry:
+ %out = shufflevector <8 x half> %src1, <8 x half> %src2, <8 x i32> <i32 0, i32 1, i32 1, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x half> %out
+}
+
+define arm_aapcs_vfpcc <8 x half> @oneoff12_f16(<8 x half> %src1, <8 x half> %src2) {
+; CHECK-LABEL: oneoff12_f16:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmovx.f16 s8, s0
+; CHECK-NEXT: vins.f16 s4, s8
+; CHECK-NEXT: vmov.f32 s5, s1
+; CHECK-NEXT: vmov.f32 s6, s2
+; CHECK-NEXT: vmov.f32 s7, s3
+; CHECK-NEXT: vmov q0, q1
+; CHECK-NEXT: bx lr
+entry:
+ %out = shufflevector <8 x half> %src1, <8 x half> %src2, <8 x i32> <i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x half> %out
+}
+
+define arm_aapcs_vfpcc <8 x half> @oneoff21_f16(<8 x half> %src1, <8 x half> %src2) {
+; CHECK-LABEL: oneoff21_f16:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vins.f16 s5, s0
+; CHECK-NEXT: vmov q0, q1
+; CHECK-NEXT: bx lr
+entry:
+ %out = shufflevector <8 x half> %src1, <8 x half> %src2, <8 x i32> <i32 8, i32 9, i32 10, i32 0, i32 12, i32 13, i32 14, i32 15>
+ ret <8 x half> %out
+}
+
+define arm_aapcs_vfpcc <8 x half> @oneoff22_f16(<8 x half> %src1, <8 x half> %src2) {
+; CHECK-LABEL: oneoff22_f16:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov q0, q1
+; CHECK-NEXT: vmovx.f16 s4, s0
+; CHECK-NEXT: vmov.f32 s0, s3
+; CHECK-NEXT: vins.f16 s0, s4
+; CHECK-NEXT: bx lr
+entry:
+ %out = shufflevector <8 x half> %src1, <8 x half> %src2, <8 x i32> <i32 14, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ ret <8 x half> %out
+}
+
+define arm_aapcs_vfpcc <8 x half> @shuffle2step_f16(<16 x half> %src) {
+; CHECKFP-LABEL: shuffle2step_f16:
+; CHECKFP: @ %bb.0: @ %entry
+; CHECKFP-NEXT: .vsave {d8}
+; CHECKFP-NEXT: vpush {d8}
+; CHECKFP-NEXT: vmovx.f16 s16, s1
+; CHECKFP-NEXT: vmovx.f16 s12, s0
+; CHECKFP-NEXT: vmov.f32 s8, s0
+; CHECKFP-NEXT: vins.f16 s12, s16
+; CHECKFP-NEXT: vins.f16 s8, s1
+; CHECKFP-NEXT: vmovx.f16 s13, s2
+; CHECKFP-NEXT: vmovx.f16 s16, s3
+; CHECKFP-NEXT: vmov.f32 s9, s2
+; CHECKFP-NEXT: vins.f16 s13, s16
+; CHECKFP-NEXT: vins.f16 s9, s3
+; CHECKFP-NEXT: vmovx.f16 s0, s5
+; CHECKFP-NEXT: vmovx.f16 s14, s4
+; CHECKFP-NEXT: vmov.f32 s10, s4
+; CHECKFP-NEXT: vins.f16 s14, s0
+; CHECKFP-NEXT: vins.f16 s10, s5
+; CHECKFP-NEXT: vmovx.f16 s0, s7
+; CHECKFP-NEXT: vmovx.f16 s15, s6
+; CHECKFP-NEXT: vins.f16 s6, s7
+; CHECKFP-NEXT: vins.f16 s15, s0
+; CHECKFP-NEXT: vmov.f32 s11, s6
+; CHECKFP-NEXT: vadd.f16 q0, q2, q3
+; CHECKFP-NEXT: vpop {d8}
+; CHECKFP-NEXT: bx lr
+entry:
+ %s1 = shufflevector <16 x half> %src, <16 x half> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
+ %s2 = shufflevector <16 x half> %src, <16 x half> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
+ %r = fadd <8 x half> %s1, %s2
+ ret <8 x half> %r
+}
+
+define arm_aapcs_vfpcc <8 x half> @shuffle3step_f16(<32 x half> %src) {
+; CHECKFP-LABEL: shuffle3step_f16:
+; CHECKFP: @ %bb.0: @ %entry
+; CHECKFP-NEXT: .save {r4, lr}
+; CHECKFP-NEXT: push {r4, lr}
+; CHECKFP-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
+; CHECKFP-NEXT: vpush {d8, d9, d10, d11, d12, d13}
+; CHECKFP-NEXT: vmovx.f16 s16, s2
+; CHECKFP-NEXT: vmov.f32 s12, s1
+; CHECKFP-NEXT: vins.f16 s12, s16
+; CHECKFP-NEXT: vmovx.f16 s16, s5
+; CHECKFP-NEXT: vmov.f32 s13, s4
+; CHECKFP-NEXT: vmovx.f16 s20, s11
+; CHECKFP-NEXT: vins.f16 s13, s16
+; CHECKFP-NEXT: vmov.f32 s19, s10
+; CHECKFP-NEXT: vins.f16 s19, s20
+; CHECKFP-NEXT: vmov.f32 s14, s7
+; CHECKFP-NEXT: vmovx.f16 s20, s8
+; CHECKFP-NEXT: vmovx.f16 s24, s1
+; CHECKFP-NEXT: vins.f16 s14, s20
+; CHECKFP-NEXT: vmov.f32 s20, s0
+; CHECKFP-NEXT: vins.f16 s20, s24
+; CHECKFP-NEXT: vmovx.f16 s24, s4
+; CHECKFP-NEXT: vmov.f32 s21, s3
+; CHECKFP-NEXT: vins.f16 s21, s24
+; CHECKFP-NEXT: vmovx.f16 s24, s7
+; CHECKFP-NEXT: vmov.f32 s22, s6
+; CHECKFP-NEXT: vins.f16 s22, s24
+; CHECKFP-NEXT: vmovx.f16 s24, s0
+; CHECKFP-NEXT: vins.f16 s24, s2
+; CHECKFP-NEXT: vmov.f32 s18, s8
+; CHECKFP-NEXT: vmovx.f16 s25, s3
+; CHECKFP-NEXT: vmovx.f16 s3, s9
+; CHECKFP-NEXT: vins.f16 s3, s11
+; CHECKFP-NEXT: vins.f16 s25, s5
+; CHECKFP-NEXT: vmov r3, s3
+; CHECKFP-NEXT: vmovx.f16 s0, s10
+; CHECKFP-NEXT: vins.f16 s9, s0
+; CHECKFP-NEXT: vmovx.f16 s2, s6
+; CHECKFP-NEXT: vins.f16 s2, s8
+; CHECKFP-NEXT: vmov r4, s24
+; CHECKFP-NEXT: vmov r0, s2
+; CHECKFP-NEXT: vmov r12, s14
+; CHECKFP-NEXT: vmov q1[2], q1[0], r4, r0
+; CHECKFP-NEXT: vmov lr, s25
+; CHECKFP-NEXT: vmov r1, s12
+; CHECKFP-NEXT: vmov q1[3], q1[1], lr, r3
+; CHECKFP-NEXT: vmov.f32 s23, s9
+; CHECKFP-NEXT: vmov q0[2], q0[0], r1, r12
+; CHECKFP-NEXT: vmov r1, s13
+; CHECKFP-NEXT: vadd.f16 q1, q5, q1
+; CHECKFP-NEXT: vmov r2, s19
+; CHECKFP-NEXT: vmov q0[3], q0[1], r1, r2
+; CHECKFP-NEXT: vadd.f16 q0, q1, q0
+; CHECKFP-NEXT: vpop {d8, d9, d10, d11, d12, d13}
+; CHECKFP-NEXT: pop {r4, pc}
+entry:
+ %s1 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>
+ %s2 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22>
+ %s3 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23>
+ %a = fadd <8 x half> %s1, %s2
+ %r = fadd <8 x half> %a, %s3
+ ret <8 x half> %r
+}
+
+define arm_aapcs_vfpcc <8 x half> @shuffle4step_f16(<32 x half> %src) {
+; CHECKFP-LABEL: shuffle4step_f16:
+; CHECKFP: @ %bb.0: @ %entry
+; CHECKFP-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14}
+; CHECKFP-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14}
+; CHECKFP-NEXT: vmovx.f16 s20, s11
+; CHECKFP-NEXT: vmovx.f16 s18, s9
+; CHECKFP-NEXT: vins.f16 s18, s20
+; CHECKFP-NEXT: vmovx.f16 s20, s15
+; CHECKFP-NEXT: vmovx.f16 s19, s13
+; CHECKFP-NEXT: vins.f16 s9, s11
+; CHECKFP-NEXT: vins.f16 s19, s20
+; CHECKFP-NEXT: vmovx.f16 s20, s3
+; CHECKFP-NEXT: vmovx.f16 s16, s1
+; CHECKFP-NEXT: vmovx.f16 s28, s10
+; CHECKFP-NEXT: vins.f16 s16, s20
+; CHECKFP-NEXT: vmovx.f16 s26, s8
+; CHECKFP-NEXT: vmovx.f16 s20, s7
+; CHECKFP-NEXT: vmovx.f16 s17, s5
+; CHECKFP-NEXT: vins.f16 s17, s20
+; CHECKFP-NEXT: vmov.f32 s22, s9
+; CHECKFP-NEXT: vins.f16 s8, s10
+; CHECKFP-NEXT: vins.f16 s13, s15
+; CHECKFP-NEXT: vins.f16 s26, s28
+; CHECKFP-NEXT: vmov.f32 s23, s13
+; CHECKFP-NEXT: vmovx.f16 s28, s14
+; CHECKFP-NEXT: vmovx.f16 s27, s12
+; CHECKFP-NEXT: vmov.f32 s10, s8
+; CHECKFP-NEXT: vins.f16 s12, s14
+; CHECKFP-NEXT: vmov.f32 s11, s12
+; CHECKFP-NEXT: vins.f16 s27, s28
+; CHECKFP-NEXT: vins.f16 s1, s3
+; CHECKFP-NEXT: vmovx.f16 s28, s2
+; CHECKFP-NEXT: vmovx.f16 s24, s0
+; CHECKFP-NEXT: vmov.f32 s20, s1
+; CHECKFP-NEXT: vins.f16 s5, s7
+; CHECKFP-NEXT: vins.f16 s24, s28
+; CHECKFP-NEXT: vmov.f32 s21, s5
+; CHECKFP-NEXT: vmovx.f16 s28, s6
+; CHECKFP-NEXT: vmovx.f16 s25, s4
+; CHECKFP-NEXT: vins.f16 s0, s2
+; CHECKFP-NEXT: vins.f16 s4, s6
+; CHECKFP-NEXT: vins.f16 s25, s28
+; CHECKFP-NEXT: vmov.f32 s1, s4
+; CHECKFP-NEXT: vadd.f16 q1, q5, q4
+; CHECKFP-NEXT: vmov.f32 s2, s10
+; CHECKFP-NEXT: vmov.f32 s3, s11
+; CHECKFP-NEXT: vadd.f16 q0, q0, q6
+; CHECKFP-NEXT: vadd.f16 q0, q0, q1
+; CHECKFP-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14}
+; CHECKFP-NEXT: bx lr
+entry:
+ %s1 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>
+ %s2 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29>
+ %s3 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30>
+ %s4 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31>
+ %a1 = fadd <8 x half> %s1, %s2
+ %a2 = fadd <8 x half> %s3, %s4
+ %r = fadd <8 x half> %a1, %a2
+ ret <8 x half> %r
+}
+
+; f64
+
define arm_aapcs_vfpcc <2 x double> @shuffle1_f64(<2 x double> %src) {
; CHECK-LABEL: shuffle1_f64:
; CHECK: @ %bb.0: @ %entry
@@ -518,7 +1695,7 @@ define arm_aapcs_vfpcc i64 @scalar_to_vector_i32(<8 x i16> %v) {
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .pad #8
; CHECK-NEXT: sub sp, #8
-; CHECK-NEXT: adr r1, .LCPI38_0
+; CHECK-NEXT: adr r1, .LCPI73_0
; CHECK-NEXT: vmov.u16 r0, q0[0]
; CHECK-NEXT: vldrw.u32 q1, [r1]
; CHECK-NEXT: vmov.32 q0[0], r0
@@ -531,7 +1708,7 @@ define arm_aapcs_vfpcc i64 @scalar_to_vector_i32(<8 x i16> %v) {
; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI38_0:
+; CHECK-NEXT: .LCPI73_0:
; CHECK-NEXT: .zero 4
; CHECK-NEXT: .long 7 @ 0x7
; CHECK-NEXT: .long 1 @ 0x1
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