[PATCH] D95866: [X86][SSE] Support variable-index float/double vector insertion on SSE41+ targets (PR47924)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: craig.topper, pengfei, spatel.
Herald added subscribers: arphaman, hiraditya.
RKSimon requested review of this revision.
Herald added a project: LLVM.

Extends D95779 <https://reviews.llvm.org/D95779> to permit insertion into float/doubles vectors while avoiding a lot of aliased memory traffic.

The scalar value is already on the simd unit, so we only need to transfer and splat the index value, then perform the select.

SSE4 codegen is a little bulky due to the tied register requirements of (non-VEX) BLENDPS/PD but the extra moves are cheap so shouldn't be an actual problem.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D95866

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/insertelement-var-index.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D95866.320769.patch
Type: text/x-patch
Size: 16307 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210202/dd4a4771/attachment.bin>