[PATCH] D95781: [RISCV] Add new vector instructions in v0.10.
Fraser Cormack via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 2 03:00:54 PST 2021
frasercrmck added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVCleanupVSETVLI.cpp:62
+ // FIXME: Consider PseudoVSETIVLI.
if (MI.getOpcode() != RISCV::PseudoVSETVLI) {
----------------
Is this currently safe, or is it a FIXME to enable additional optimizations? It might be reassuring to have some tests which show `vsetvli` and `vsetivli` behave correctly together.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D95781/new/
https://reviews.llvm.org/D95781
More information about the llvm-commits
mailing list