[llvm] 6442198 - [ARM] Regenerate LowOverheadLoops mir tests. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 2 02:29:11 PST 2021
Author: David Green
Date: 2021-02-02T10:28:58Z
New Revision: 64421988e3958b19a8db6d29433f62f3db2fdb9a
URL: https://github.com/llvm/llvm-project/commit/64421988e3958b19a8db6d29433f62f3db2fdb9a
DIFF: https://github.com/llvm/llvm-project/commit/64421988e3958b19a8db6d29433f62f3db2fdb9a.diff
LOG: [ARM] Regenerate LowOverheadLoops mir tests. NFC
Added:
Modified:
llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-chain.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-prev-iteration.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix-debug.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/out-of-range-cbz.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-def.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir
index c65dc8e3af45..fa439a6ca44b 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir
@@ -91,6 +91,7 @@ body: |
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
+ ; CHECK: dead $lr = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: $lr = t2DLS killed $r0
; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14 /* CC::al */, $noreg
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir
index 5e4c960a6413..086119f320ad 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir
@@ -133,6 +133,7 @@ body: |
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: $sp = frame-setup tSUBspi $sp, 8, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 40
+ ; CHECK: dead $lr = tMOVr renamable $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
@@ -152,7 +153,7 @@ body: |
; CHECK: early-clobber renamable $r3 = t2STR_PRE killed renamable $r1, killed renamable $r3, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep3)
; CHECK: $r1 = tLDRspi $sp, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.7)
; CHECK: $lr = tMOVr killed $r1, 14 /* CC::al */, $noreg
- ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr
+ ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr
; CHECK: $r12 = tMOVr killed $lr, 14 /* CC::al */, $noreg
; CHECK: tSTRspi killed $r0, $sp, 7, 14 /* CC::al */, $noreg :: (store 4 into %stack.0)
; CHECK: tSTRspi killed $r2, $sp, 6, 14 /* CC::al */, $noreg :: (store 4 into %stack.1)
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-chain.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-chain.mir
index 60ee6d61d3ff..bcb901188c8b 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-chain.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-chain.mir
@@ -260,6 +260,7 @@ body: |
; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r8 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: dead $lr = tMOVr renamable $r3, 14 /* CC::al */, $noreg
; CHECK: $r12 = tMOVr killed $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: bb.4.bb28:
@@ -272,7 +273,7 @@ body: |
; CHECK: renamable $r8 = nuw t2ADDri killed renamable $r8, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r5, dead $cpsr = tEOR killed renamable $r5, killed renamable $r6, 14 /* CC::al */, $noreg
; CHECK: renamable $r6 = tLDRr renamable $r0, $r3, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep219)
- ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r12 = tMOVr $lr, 14 /* CC::al */, $noreg
; CHECK: renamable $r5 = nsw tADDhirr killed renamable $r5, killed renamable $r6, 14 /* CC::al */, $noreg
; CHECK: tSTRr killed renamable $r5, renamable $r0, $r3, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep219)
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-prev-iteration.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-prev-iteration.mir
index 7662bb5ae037..1f66911983d2 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-prev-iteration.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-prev-iteration.mir
@@ -274,6 +274,7 @@ body: |
; CHECK: renamable $r5 = tLDRr renamable $r1, $r3, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep617)
; CHECK: renamable $r7, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $r6 = tLDRr renamable $r2, $r3, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep418)
+ ; CHECK: dead $r12 = tMOVr $lr, 14 /* CC::al */, $noreg
; CHECK: renamable $r8 = nuw t2ADDri killed renamable $r8, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r5, dead $cpsr = tEOR killed renamable $r5, killed renamable $r6, 14 /* CC::al */, $noreg
; CHECK: renamable $r6 = tLDRr renamable $r0, $r3, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep219)
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir
index cdaeeced89d8..94bcca05a3ad 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir
@@ -123,6 +123,7 @@ body: |
; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg
+ ; CHECK: dead $lr = tMOVr $r3, 14 /* CC::al */, $noreg
; CHECK: $lr = tMOVr killed $r3, 14 /* CC::al */, $noreg
; CHECK: bb.2.for.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
@@ -132,7 +133,7 @@ body: |
; CHECK: renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep7)
; CHECK: renamable $r3 = nsw t2MUL killed renamable $r3, killed renamable $r12, 14 /* CC::al */, $noreg
; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep11)
- ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr
+ ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr
; CHECK: t2Bcc %bb.2, 1 /* CC::ne */, killed $cpsr
; CHECK: tB %bb.3, 14 /* CC::al */, $noreg
; CHECK: bb.3.for.cond.cleanup:
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix-debug.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix-debug.mir
index 843ec0089c12..df150cb32112 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix-debug.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix-debug.mir
@@ -249,6 +249,7 @@ body: |
; CHECK: renamable $r2 = t2LDRs renamable $r9, renamable $r1, 2, 14 /* CC::al */, $noreg, debug-location !41 :: (load 4 from %ir.arrayidx7.us)
; CHECK: $r3 = tMOVr $r5, 14 /* CC::al */, $noreg, debug-location !32
; CHECK: $r0 = tMOVr $r8, 14 /* CC::al */, $noreg, debug-location !32
+ ; CHECK: dead $lr = tMOVr $r10, 14 /* CC::al */, $noreg, debug-location !32
; CHECK: $lr = t2DLS renamable $r10, debug-location !42
; CHECK: bb.3.for.body3.us:
; CHECK: successors: %bb.3(0x7c000000), %bb.4(0x04000000)
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir
index 0acad61f8be3..e9d6e33f9b4c 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir
@@ -237,6 +237,7 @@ body: |
; CHECK: renamable $r6, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: renamable $r2 = IMPLICIT_DEF
; CHECK: $r10 = tMOVr $r0, 14 /* CC::al */, $noreg
+ ; CHECK: dead $lr = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: $lr = t2DLS killed renamable $r0
; CHECK: bb.2.for.body.i:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
@@ -284,6 +285,7 @@ body: |
; CHECK: renamable $q1 = MVE_VMOV_to_lane_32 killed renamable $q1, killed renamable $r1, 0, 14 /* CC::al */, $noreg
; CHECK: $r6 = tMOVr $r5, 14 /* CC::al */, $noreg
; CHECK: $r1 = tMOVr $r8, 14 /* CC::al */, $noreg
+ ; CHECK: dead $lr = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: $lr = t2DLS renamable $r0
; CHECK: bb.6.vector.body:
; CHECK: successors: %bb.6(0x7c000000), %bb.7(0x04000000)
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir
index 075df0200eee..0c0bf0234be3 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir
@@ -119,6 +119,7 @@ body: |
; CHECK: bb.1.for.body.preheader:
; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3
+ ; CHECK: dead $lr = tMOVr $r3, 14 /* CC::al */, $noreg
; CHECK: $lr = tMOVr killed $r3, 14 /* CC::al */, $noreg
; CHECK: tB %bb.2, 14 /* CC::al */, $noreg
; CHECK: bb.2.for.end:
@@ -127,7 +128,7 @@ body: |
; CHECK: renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg
- ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr
+ ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr
; CHECK: tBcc %bb.3, 1 /* CC::ne */, killed $cpsr
; CHECK: t2B %bb.5, 14 /* CC::al */, $noreg
; CHECK: bb.3.for.body:
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/out-of-range-cbz.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/out-of-range-cbz.mir
index 46c2e1a812df..eae88ce6e9bb 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/out-of-range-cbz.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/out-of-range-cbz.mir
@@ -195,7 +195,7 @@ body: |
; CHECK: bb.4.if.end:
; CHECK: liveins: $r1, $r3
; CHECK: tSTRi killed renamable $r3, killed renamable $r1, 0, 14 /* CC::al */, $noreg :: (store 4 into @e)
- ; CHECK: INLINEASM &"", 1
+ ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
; CHECK: bb.5.j.us.us.preheader:
; CHECK: successors: %bb.6(0x80000000)
@@ -219,54 +219,54 @@ body: |
; CHECK: bb.7.if.end.us.us.us:
; CHECK: successors: %bb.8(0x40000000), %bb.6(0x40000000)
; CHECK: liveins: $lr, $r2, $r12
- ; CHECK: INLINEASM &"", 1
+ ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */
; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14 /* CC::al */, $noreg :: (dereferenceable load 4 from @d)
; CHECK: tCBZ $r3, %bb.8
; CHECK: t2LE %bb.6
; CHECK: bb.8.if.end.us.us.us.1:
; CHECK: successors: %bb.9(0x40000000), %bb.6(0x40000000)
; CHECK: liveins: $lr, $r2, $r12
- ; CHECK: INLINEASM &"", 1
+ ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */
; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14 /* CC::al */, $noreg :: (dereferenceable load 4 from @d)
; CHECK: tCBZ $r3, %bb.9
; CHECK: t2LE %bb.6
; CHECK: bb.9.if.end.us.us.us.2:
; CHECK: successors: %bb.10(0x40000000), %bb.6(0x40000000)
; CHECK: liveins: $lr, $r2, $r12
- ; CHECK: INLINEASM &"", 1
+ ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */
; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14 /* CC::al */, $noreg :: (dereferenceable load 4 from @d)
; CHECK: tCBZ $r3, %bb.10
; CHECK: t2LE %bb.6
; CHECK: bb.10.if.end.us.us.us.3:
; CHECK: successors: %bb.11(0x40000000), %bb.6(0x40000000)
; CHECK: liveins: $lr, $r2, $r12
- ; CHECK: INLINEASM &"", 1
+ ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */
; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14 /* CC::al */, $noreg :: (dereferenceable load 4 from @d)
; CHECK: tCBZ $r3, %bb.11
; CHECK: t2LE %bb.6
; CHECK: bb.11.if.end.us.us.us.4:
; CHECK: successors: %bb.12(0x40000000), %bb.6(0x40000000)
; CHECK: liveins: $lr, $r2, $r12
- ; CHECK: INLINEASM &"", 1
+ ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */
; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14 /* CC::al */, $noreg :: (dereferenceable load 4 from @d)
; CHECK: tCBZ $r3, %bb.12
; CHECK: t2LE %bb.6
; CHECK: bb.12.if.end.us.us.us.5:
; CHECK: successors: %bb.13(0x40000000), %bb.6(0x40000000)
; CHECK: liveins: $lr, $r2, $r12
- ; CHECK: INLINEASM &"", 1
+ ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */
; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14 /* CC::al */, $noreg :: (dereferenceable load 4 from @d)
; CHECK: tCBZ $r3, %bb.13
; CHECK: t2LE %bb.6
; CHECK: bb.13.if.end.us.us.us.6:
; CHECK: successors: %bb.14(0x04000000), %bb.6(0x7c000000)
; CHECK: liveins: $lr, $r2, $r12
- ; CHECK: INLINEASM &"", 1
+ ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */
; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14 /* CC::al */, $noreg :: (dereferenceable load 4 from @d)
; CHECK: tCBZ $r3, %bb.14
; CHECK: t2LE %bb.6
; CHECK: bb.14.if.end.us.us.us.7:
- ; CHECK: INLINEASM &"", 1
+ ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
; CHECK: bb.15.j.us27.preheader:
; CHECK: successors: %bb.16(0x80000000)
@@ -289,7 +289,7 @@ body: |
; CHECK: bb.17.if.end.us38:
; CHECK: liveins: $r1, $r3
; CHECK: tSTRi killed renamable $r3, killed renamable $r1, 0, 14 /* CC::al */, $noreg :: (store 4 into @e)
- ; CHECK: INLINEASM &"", 1
+ ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.entry:
successors: %bb.1(0x30000000), %bb.11(0x50000000)
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir
index 42233f3fc412..b456dc63654d 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir
@@ -175,6 +175,7 @@ body: |
; CHECK: renamable $r7, dead $cpsr = tSUBrr renamable $r2, renamable $r4, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2ADDrs renamable $r0, renamable $r4, 18, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: dead $lr = tMOVr renamable $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg
; CHECK: $r5 = tMOVr killed $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = t2ADDrs renamable $r1, renamable $r4, 18, 14 /* CC::al */, $noreg, $noreg
@@ -186,7 +187,7 @@ body: |
; CHECK: $lr = tMOVr killed $r5, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VABSf32 killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: renamable $r1 = MVE_VSTRBU8_pre killed renamable $q0, killed renamable $r1, 16, 0, $noreg :: (store 16 into %ir.scevgep13, align 4)
- ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr
+ ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr
; CHECK: $r5 = tMOVr killed $lr, 14 /* CC::al */, $noreg
; CHECK: tBcc %bb.4, 1 /* CC::ne */, killed $cpsr
; CHECK: tB %bb.5, 14 /* CC::al */, $noreg
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir
index a7028dde74ed..8126e0b8257f 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir
@@ -117,7 +117,7 @@ body: |
; CHECK: dead renamable $r2 = SPACE 4096, undef renamable $r0
; CHECK: renamable $r2, renamable $r0 = t2LDR_PRE killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep)
; CHECK: early-clobber renamable $r1 = t2STR_PRE killed renamable $r2, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep1)
- ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr
+ ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr
; CHECK: t2Bcc %bb.2, 1 /* CC::ne */, killed $cpsr
; CHECK: tB %bb.3, 14 /* CC::al */, $noreg
; CHECK: bb.3.if.end:
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir
index 21efcc1bf2dd..1d3ce980b9f5 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir
@@ -123,6 +123,7 @@ body: |
; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg
+ ; CHECK: dead $lr = tMOVr $r3, 14 /* CC::al */, $noreg
; CHECK: $lr = t2DLS killed $r3
; CHECK: bb.2.for.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-def.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-def.mir
index 11197b5514be..6cc34fee6ff3 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-def.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-def.mir
@@ -103,12 +103,13 @@ body: |
; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r2 = t2LSRri renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: $lr = tMOVr renamable $lr, 14 /* CC::al */, $noreg
; CHECK: bb.1.while.body:
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2
; CHECK: renamable $r3, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep7)
; CHECK: tCMPhir renamable $lr, renamable $r2, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2IT 2, 8, implicit-def $itstate
; CHECK: renamable $r3 = tLSRri $noreg, killed renamable $r3, 1, 2 /* CC::hs */, killed $cpsr, implicit renamable $r3, implicit killed $itstate
; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep4)
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir
index 4ba73cd288f3..3356fa84a348 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir
@@ -101,6 +101,7 @@ body: |
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14 /* CC::al */, $noreg
+ ; CHECK: dead $lr = tMOVr renamable $r0, 14 /* CC::al */, $noreg
; CHECK: renamable $r2 = t2LSRri renamable $r0, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $lr = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: bb.1.while.body:
@@ -108,7 +109,7 @@ body: |
; CHECK: liveins: $lr, $r0, $r1, $r2
; CHECK: renamable $r3, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep7)
; CHECK: tCMPhir renamable $lr, renamable $r2, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2IT 2, 8, implicit-def $itstate
; CHECK: renamable $r3 = tLSRri $noreg, killed renamable $r3, 1, 2 /* CC::hs */, killed $cpsr, implicit killed renamable $r3, implicit killed $itstate
; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep4)
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