[llvm] 3a46502 - Move step to PreLegalizer
Thomas Symalla via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 2 00:16:17 PST 2021
Author: Thomas Symalla
Date: 2021-02-02T09:14:53+01:00
New Revision: 3a46502264b6a53764e28d55e990f714a31cba70
URL: https://github.com/llvm/llvm-project/commit/3a46502264b6a53764e28d55e990f714a31cba70
DIFF: https://github.com/llvm/llvm-project/commit/3a46502264b6a53764e28d55e990f714a31cba70.diff
LOG: Move step to PreLegalizer
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
index f0c180b68b8e..23ef4ed93ead 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
@@ -80,12 +80,18 @@ bool AMDGPUPreLegalizerCombinerHelper::matchClampI64ToI16(
Register Base;
// match max / min pattern
- if (!mi_match(MI.getOperand(1).getReg(), MRI, m_GSMin(m_Reg(Base), m_ICst(MatchInfo.Cmp1))))
- return false;
-
- if (!mi_match(Base, MRI, m_GSMax(m_Reg(MatchInfo.Origin), m_ICst(MatchInfo.Cmp2))))
- return false;
+ if (mi_match(MI.getOperand(1).getReg(), MRI, m_GSMin(m_Reg(Base), m_ICst(MatchInfo.Cmp1)))) {
+ if (!mi_match(Base, MRI, m_GSMax(m_Reg(MatchInfo.Origin), m_ICst(MatchInfo.Cmp2)))) {
+ return false;
+ }
+ }
+ if (mi_match(MI.getOperand(1).getReg(), MRI, m_GSMax(m_Reg(Base), m_ICst(MatchInfo.Cmp1)))) {
+ if (!mi_match(Base, MRI, m_GSMin(m_Reg(MatchInfo.Origin), m_ICst(MatchInfo.Cmp2)))) {
+ return false;
+ }
+ }
+
const auto Cmp1 = MatchInfo.Cmp1;
const auto Cmp2 = MatchInfo.Cmp2;
const auto Diff = std::abs(Cmp2 - Cmp1);
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
index 492318d37f57..8b8b5d5fd93c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
@@ -8,9 +8,9 @@ declare i64 @llvm.smin.i64(i64, i64)
; GFX10-LABEL: {{^}}v_clamp_i64_i16
; GFX678: v_cvt_pk_i16_i32_e32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
; GFX9: v_cvt_pk_i16_i32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
-; GFX6789: v_mov_b32_e32 [[B]], 0xffff8000
-; GFX6789: v_mov_b32_e32 [[C:v[0-9]+]], 0x7fff
-; GFX6789: v_med3_i32 [[A]], [[B]], [[A]], [[C]]
+; GFX6789: v_mov_b32_e32 [[B]], 0x7fff
+; GFX6789: v_mov_b32_e32 [[C:v[0-9]+]], 0xffff8000
+; GFX6789: v_med3_i32 [[A]], [[C]], [[A]], [[B]]
; GFX10: v_cvt_pk_i16_i32_e64 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
; GFX10: v_mov_b32_e32 [[C:v[0-9]+]], 0xffff8000
; GFX10: v_med3_i32 [[A]], [[C]], [[A]], 0x7fff
@@ -25,28 +25,28 @@ entry:
; GFX10-LABEL: {{^}}v_clamp_i64_i16_reverse
; GFX678: v_cvt_pk_i16_i32_e32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
; GFX9: v_cvt_pk_i16_i32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
-; GFX6789: v_mov_b32_e32 [[B]], 0xffff8000
-; GFX6789: v_mov_b32_e32 [[C:v[0-9]+]], 0x7fff
-; GFX6789: v_med3_i32 [[A]], [[B]], [[A]], [[C]]
+; GFX6789: v_mov_b32_e32 [[B]], 0x7fff
+; GFX6789: v_mov_b32_e32 [[C:v[0-9]+]], 0xffff8000
+; GFX6789: v_med3_i32 [[A]], [[C]], [[A]], [[B]]
; GFX10: v_cvt_pk_i16_i32_e64 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
-; GFX10: v_mov_b32_e32 [[C:v[0-9]+]], 0x7fff
-; GFX10: v_med3_i32 [[A]], 0xffff8000, [[A]], [[C]]
+; GFX10: v_mov_b32_e32 [[C:v[0-9]+]], 0xffff8000
+; GFX10: v_med3_i32 [[A]], [[C]], [[A]], 0x7fff
define i16 @v_clamp_i64_i16_reverse(i64 %in) #0 {
entry:
%min = call i64 @llvm.smin.i64(i64 %in, i64 32767)
%max = call i64 @llvm.smax.i64(i64 %min, i64 -32768)
- %result = trunc i64 %min to i16
+ %result = trunc i64 %max to i16
ret i16 %result
}
-; GFX10-LABEL: {{^}}v_clamp_i64_i16_wrong_lower
+; GFX10-LABEL: {{^}}v_clamp_i64_i16_invalid_lower
; GFX6789: v_mov_b32_e32 [[B:v[0-9]+]], 0x8001
; GFX6789: v_cndmask_b32_e32 [[A:v[0-9]+]], [[B]], [[A]], vcc
; GFX6789: v_cndmask_b32_e32 [[C:v[0-9]+]], 0, [[C]], vcc
; GFX10: v_cndmask_b32_e32 [[A:v[0-9]+]], 0x8001, [[A]], vcc_lo
; GFX10: v_cndmask_b32_e32 [[B:v[0-9]+]], 0, [[B]], vcc_lo
-define i16 @v_clamp_i64_i16_wrong_lower(i64 %in) #0 {
+define i16 @v_clamp_i64_i16_invalid_lower(i64 %in) #0 {
entry:
%min = call i64 @llvm.smin.i64(i64 %in, i64 32769)
%max = call i64 @llvm.smax.i64(i64 %min, i64 -32768)
@@ -69,12 +69,12 @@ entry:
; GFX10-LABEL: {{^}}v_clamp_i64_i16_lower_than_short
; GFX678: v_cvt_pk_i16_i32_e32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
; GFX9: v_cvt_pk_i16_i32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
-; GFX6789: v_mov_b32_e32 [[B]], 0xffffff01
-; GFX6789: v_mov_b32_e32 [[C:v[0-9]+]], 0x100
-; GFX6789: v_med3_i32 [[A]], [[B]], [[A]], [[C]]
+; GFX6789: v_mov_b32_e32 [[B]], 0x100
+; GFX6789: v_mov_b32_e32 [[C:v[0-9]+]], 0xffffff01
+; GFX6789: v_med3_i32 [[A]], [[C]], [[A]], [[B]]
; GFX10: v_cvt_pk_i16_i32_e64 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
-; GFX10: v_mov_b32_e32 [[C:v[0-9]+]], 0x100
-; GFX10: v_med3_i32 [[A]], 0xffffff01, [[A]], [[C]]
+; GFX10: v_mov_b32_e32 [[C:v[0-9]+]], 0xffffff01
+; GFX10: v_med3_i32 [[A]], [[C]], [[A]], 0x100
define i16 @v_clamp_i64_i16_lower_than_short(i64 %in) #0 {
entry:
%min = call i64 @llvm.smin.i64(i64 %in, i64 256)
@@ -86,12 +86,12 @@ entry:
; GFX10-LABEL: {{^}}v_clamp_i64_i16_lower_than_short_reverse
; GFX678: v_cvt_pk_i16_i32_e32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
; GFX9: v_cvt_pk_i16_i32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
-; GFX6789: v_mov_b32_e32 [[B]], 0xffffff01
-; GFX6789: v_mov_b32_e32 [[C:v[0-9]+]], 0x100
-; GFX6789: v_med3_i32 [[A]], [[B]], [[A]], [[C]]
+; GFX6789: v_mov_b32_e32 [[B]], 0x100
+; GFX6789: v_mov_b32_e32 [[C:v[0-9]+]], 0xffffff01
+; GFX6789: v_med3_i32 [[A]], [[C]], [[A]], [[B]]
; GFX10: v_cvt_pk_i16_i32_e64 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
-; GFX10: v_mov_b32_e32 [[C:v[0-9]+]], 0x100
-; GFX10: v_med3_i32 [[A]], 0xffffff01, [[A]], [[C]]
+; GFX10: v_mov_b32_e32 [[C:v[0-9]+]], 0xffffff01
+; GFX10: v_med3_i32 [[A]], [[C]], [[A]], 0x100
define i16 @v_clamp_i64_i16_lower_than_short_reverse(i64 %in) #0 {
entry:
%max = call i64 @llvm.smax.i64(i64 %in, i64 -255)
@@ -101,12 +101,12 @@ entry:
}
; GFX10-LABEL: {{^}}v_clamp_i64_i16_zero
-; GFX678: v_mov_b32_e32 [[A:v[0-9]+]], 0
-; GFX10: v_mov_b32_e32 [[A:v[0-9]+]], 0
+; GFX6789: v_mov_b32_e32 v0, 0
+; GFX10: v_cmp_lt_i64_e32 vcc_lo, 0, v[0:1]
define i16 @v_clamp_i64_i16_zero(i64 %in) #0 {
entry:
%max = call i64 @llvm.smax.i64(i64 %in, i64 0)
%min = call i64 @llvm.smin.i64(i64 %max, i64 0)
- %result = trunc i64 %max to i16
+ %result = trunc i64 %min to i16
ret i16 %result
}
\ No newline at end of file
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