[llvm] dae85e4 - Fixed the lit tests and a bug in the implementation.
Thomas Symalla via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 2 00:16:08 PST 2021
Author: Thomas Symalla
Date: 2021-02-02T09:14:52+01:00
New Revision: dae85e4671416490c6aaf2bac88c3ce1d74cc4d6
URL: https://github.com/llvm/llvm-project/commit/dae85e4671416490c6aaf2bac88c3ce1d74cc4d6
DIFF: https://github.com/llvm/llvm-project/commit/dae85e4671416490c6aaf2bac88c3ce1d74cc4d6.diff
LOG: Fixed the lit tests and a bug in the implementation.
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
index 8996a45e5dd1..3724b69f5821 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
@@ -291,7 +291,7 @@ bool AMDGPUPostLegalizerCombinerHelper::matchClampI64ToI16(
CmpInst::Predicate Predicate2;
- if (!mi_match(Base, MRI, m_GISelect(m_GICmp(m_Pred(Predicate2), m_Reg(), m_Reg()), m_Reg(MatchInfo.AssignValue), m_ICst(MatchInfo.Cmp2))))
+ if (!mi_match(Base, MRI, m_GISelect(m_GICmp(m_Pred(Predicate2), m_Reg(), m_Reg()), m_Reg(MatchInfo.Origin), m_ICst(MatchInfo.Cmp2))))
return false;
if ((Predicate1 == CmpInst::ICMP_SLT &&
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
index 6cf6d95e294c..dd809f9b6a77 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
@@ -1,6 +1,6 @@
-; RUN: llc -global-isel -mcpu=tahiti -mtriple=amdGFX10-amd-amdhsa -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX678,GFX6789 %s
-; RUN: llc -global-isel -mcpu=gfx900 -mtriple=amdGFX10-amd-amdhsa -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX9,GFX6789 %s
-; RUN: llc -global-isel -mcpu=gfx1010 -march=amdGFX10 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10 %s
+; RUN: llc -global-isel -mcpu=tahiti -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX678,GFX6789 %s
+; RUN: llc -global-isel -mcpu=gfx900 -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX9,GFX6789 %s
+; RUN: llc -global-isel -mcpu=gfx1010 -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10 %s
; GFX10-LABEL: {{^}}v_clamp_i64_i16
; GFX678: v_cvt_pk_i16_i32_e32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
@@ -11,15 +11,14 @@
; GFX10: v_cvt_pk_i16_i32_e64 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
; GFX10: v_mov_b32_e32 [[C:v[0-9]+]], 0x7fff
; GFX10: v_med3_i32 [[A]], 0xffff8000, [[A]], [[C]]
-define i16 @v_clamp_i64_i16(i64 %in) nounwind {
+define i16 @v_clamp_i64_i16(i64 %in) #0 {
entry:
- %0 = icmp sgt i64 %in, -32768
- %1 = select i1 %0, i64 %in, i64 -32768
- %2 = icmp slt i64 %1, 32767
- %3 = select i1 %2, i64 %1, i64 32767
- %4 = trunc i64 %3 to i16
-
- ret i16 %4
+ %i = icmp sgt i64 %in, -32768
+ %i1 = select i1 %i, i64 %in, i64 -32768
+ %i2 = icmp slt i64 %i1, 32767
+ %i3 = select i1 %i2, i64 %i1, i64 32767
+ %i4 = trunc i64 %i3 to i16
+ ret i16 %i4
}
; GFX10-LABEL: {{^}}v_clamp_i64_i16_reverse
@@ -31,15 +30,14 @@ entry:
; GFX10: v_cvt_pk_i16_i32_e64 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
; GFX10: v_mov_b32_e32 [[C:v[0-9]+]], 0x7fff
; GFX10: v_med3_i32 [[A]], 0xffff8000, [[A]], [[C]]
-define i16 @v_clamp_i64_i16_reverse(i64 %in) nounwind {
+define i16 @v_clamp_i64_i16_reverse(i64 %in) #0 {
entry:
- %0 = icmp slt i64 %in, 32767
- %1 = select i1 %0, i64 %in, i64 32767
- %2 = icmp sgt i64 %1, -32768
- %3 = select i1 %2, i64 %1, i64 -32768
- %4 = trunc i64 %3 to i16
-
- ret i16 %4
+ %i = icmp slt i64 %in, 32767
+ %i1 = select i1 %i, i64 %in, i64 32767
+ %i2 = icmp sgt i64 %i1, -32768
+ %i3 = select i1 %i2, i64 %i1, i64 -32768
+ %i4 = trunc i64 %i3 to i16
+ ret i16 %i4
}
; GFX10-LABEL: {{^}}v_clamp_i64_i16_wrong_lower
@@ -49,31 +47,28 @@ entry:
; GFX10: v_cndmask_b32_e32 [[A:v[0-9]+]], 0x8001, [[A]], vcc_lo
; GFX10: v_cndmask_b32_e32 [[B:v[0-9]+]], 0, [[B]], vcc_lo
-define i16 @v_clamp_i64_i16_wrong_lower(i64 %in) nounwind {
+define i16 @v_clamp_i64_i16_wrong_lower(i64 %in) #0 {
entry:
- %0 = icmp slt i64 %in, 32769
- %1 = select i1 %0, i64 %in, i64 32769
- %2 = icmp sgt i64 %1, -32768
- %3 = select i1 %2, i64 %1, i64 -32768
- %4 = trunc i64 %3 to i16
-
- ret i16 %4
+ %i = icmp slt i64 %in, 32769
+ %i1 = select i1 %i, i64 %in, i64 32769
+ %i2 = icmp sgt i64 %i1, -32768
+ %i3 = select i1 %i2, i64 %i1, i64 -32768
+ %i4 = trunc i64 %i3 to i16
+ ret i16 %i4
}
; GFX10-LABEL: {{^}}v_clamp_i64_i16_wrong_lower_and_higher
; GFX6789: v_mov_b32_e32 [[B:v[0-9]+]], 0x8000
; GFX6789: v_cndmask_b32_e32 [[A:v[0-9]+]], [[B]], [[A]], vcc
-
; GFX10: v_cndmask_b32_e32 [[A:v[0-9]+]], 0x8000, [[A]], vcc_lo
-define i16 @v_clamp_i64_i16_wrong_lower_and_higher(i64 %in) nounwind {
+define i16 @v_clamp_i64_i16_wrong_lower_and_higher(i64 %in) #0 {
entry:
- %0 = icmp sgt i64 %in, -32769
- %1 = select i1 %0, i64 %in, i64 -32769
- %2 = icmp slt i64 %1, 32768
- %3 = select i1 %2, i64 %1, i64 32768
- %4 = trunc i64 %3 to i16
-
- ret i16 %4
+ %i = icmp sgt i64 %in, -32769
+ %i1 = select i1 %i, i64 %in, i64 -32769
+ %i2 = icmp slt i64 %i1, 32768
+ %i3 = select i1 %i2, i64 %i1, i64 32768
+ %i4 = trunc i64 %i3 to i16
+ ret i16 %i4
}
; GFX10-LABEL: {{^}}v_clamp_i64_i16_lower_than_short
@@ -85,15 +80,14 @@ entry:
; GFX10: v_cvt_pk_i16_i32_e64 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
; GFX10: v_mov_b32_e32 [[C:v[0-9]+]], 0x100
; GFX10: v_med3_i32 [[A]], 0xffffff01, [[A]], [[C]]
-define i16 @v_clamp_i64_i16_lower_than_short(i64 %in) nounwind {
+define i16 @v_clamp_i64_i16_lower_than_short(i64 %in) #0 {
entry:
- %0 = icmp slt i64 %in, 256
- %1 = select i1 %0, i64 %in, i64 256
- %2 = icmp sgt i64 %1, -255
- %3 = select i1 %2, i64 %1, i64 -255
- %4 = trunc i64 %3 to i16
-
- ret i16 %4
+ %i = icmp slt i64 %in, 256
+ %i1 = select i1 %i, i64 %in, i64 256
+ %i2 = icmp sgt i64 %i1, -255
+ %i3 = select i1 %i2, i64 %i1, i64 -255
+ %i4 = trunc i64 %i3 to i16
+ ret i16 %i4
}
; GFX10-LABEL: {{^}}v_clamp_i64_i16_lower_than_short_reverse
@@ -105,27 +99,25 @@ entry:
; GFX10: v_cvt_pk_i16_i32_e64 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
; GFX10: v_mov_b32_e32 [[C:v[0-9]+]], 0x100
; GFX10: v_med3_i32 [[A]], 0xffffff01, [[A]], [[C]]
-define i16 @v_clamp_i64_i16_lower_than_short_reverse(i64 %in) nounwind {
+define i16 @v_clamp_i64_i16_lower_than_short_reverse(i64 %in) #0 {
entry:
- %0 = icmp sgt i64 %in, -255
- %1 = select i1 %0, i64 %in, i64 -255
- %2 = icmp slt i64 %1, 256
- %3 = select i1 %2, i64 %1, i64 256
- %4 = trunc i64 %3 to i16
-
- ret i16 %4
+ %i = icmp sgt i64 %in, -255
+ %i1 = select i1 %i, i64 %in, i64 -255
+ %i2 = icmp slt i64 %i1, 256
+ %i3 = select i1 %i2, i64 %i1, i64 256
+ %i4 = trunc i64 %i3 to i16
+ ret i16 %i4
}
; GFX10-LABEL: {{^}}v_clamp_i64_i16_zero
; GFX678: v_mov_b32_e32 [[A:v[0-9]+]], 0
; GFX10: v_mov_b32_e32 [[A:v[0-9]+]], 0
-define i16 @v_clamp_i64_i16_zero(i64 %in) nounwind {
+define i16 @v_clamp_i64_i16_zero(i64 %in) #0 {
entry:
- %0 = icmp sgt i64 %in, 0
- %1 = select i1 %0, i64 %in, i64 0
- %2 = icmp slt i64 %1, 0
- %3 = select i1 %2, i64 %1, i64 0
- %4 = trunc i64 %3 to i16
-
- ret i16 %4
+ %i = icmp sgt i64 %in, 0
+ %i1 = select i1 %i, i64 %in, i64 0
+ %i2 = icmp slt i64 %i1, 0
+ %i3 = select i1 %i2, i64 %i1, i64 0
+ %i4 = trunc i64 %i3 to i16
+ ret i16 %i4
}
\ No newline at end of file
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