[llvm] d41b7fa - Renames
Thomas Symalla via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 2 00:16:03 PST 2021
Author: Thomas Symalla
Date: 2021-02-02T09:14:52+01:00
New Revision: d41b7fa9bf80e09a52aa0d392db94a7b971044c9
URL: https://github.com/llvm/llvm-project/commit/d41b7fa9bf80e09a52aa0d392db94a7b971044c9
DIFF: https://github.com/llvm/llvm-project/commit/d41b7fa9bf80e09a52aa0d392db94a7b971044c9.diff
LOG: Renames
Added:
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
Modified:
llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
Removed:
llvm/test/CodeGen/AMDGPU/GlobalISel/clampi64toi16.ll
################################################################################
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h b/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
index 189272a3eb61..c91462f9745a 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
@@ -492,12 +492,12 @@ m_Not(const SrcTy &&Src) {
}
template <typename Boundary1, typename Boundary2, typename Origin>
-struct MaxMin_match_helper {
+struct maxmin_match_helper {
Boundary1 B1;
Boundary2 B2;
Origin O;
- MaxMin_match_helper(const Boundary1 &FirstBoundary,
+ maxmin_match_helper(const Boundary1 &FirstBoundary,
const Boundary2 &SecondBoundary, const Origin &Or)
: B1(FirstBoundary), B2(SecondBoundary), O(Or) {}
@@ -528,9 +528,9 @@ struct MaxMin_match_helper {
};
template <typename Boundary1, typename Boundary2, typename Origin>
-inline MaxMin_match_helper<Boundary1, Boundary2, Origin>
+inline maxmin_match_helper<Boundary1, Boundary2, Origin>
m_MaxMin(const Boundary1 &B1, const Boundary2 &B2, const Origin &O) {
- return MaxMin_match_helper<Boundary1, Boundary2, Origin>(B1, B2, O);
+ return maxmin_match_helper<Boundary1, Boundary2, Origin>(B1, B2, O);
}
} // namespace MIPatternMatch
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/clampi64toi16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
similarity index 66%
rename from llvm/test/CodeGen/AMDGPU/GlobalISel/clampi64toi16.ll
rename to llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
index 763b50d79605..6cf6d95e294c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/clampi64toi16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
@@ -1,16 +1,16 @@
-; RUN: llc -global-isel -mcpu=tahiti -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX678,GFX6789 %s
-; RUN: llc -global-isel -mcpu=gfx900 -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX9,GFX6789 %s
-; RUN: llc -global-isel -mcpu=gfx1010 -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
+; RUN: llc -global-isel -mcpu=tahiti -mtriple=amdGFX10-amd-amdhsa -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX678,GFX6789 %s
+; RUN: llc -global-isel -mcpu=gfx900 -mtriple=amdGFX10-amd-amdhsa -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX9,GFX6789 %s
+; RUN: llc -global-isel -mcpu=gfx1010 -march=amdGFX10 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10 %s
-; GCN-LABEL: {{^}}v_clamp_i64_i16
+; GFX10-LABEL: {{^}}v_clamp_i64_i16
; GFX678: v_cvt_pk_i16_i32_e32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
; GFX9: v_cvt_pk_i16_i32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
; GFX6789: v_mov_b32_e32 [[B]], 0xffff8000
; GFX6789: v_mov_b32_e32 [[C:v[0-9]+]], 0x7fff
; GFX6789: v_med3_i32 [[A]], [[B]], [[A]], [[C]]
-; GCN: v_cvt_pk_i16_i32_e64 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
-; GCN: v_mov_b32_e32 [[C:v[0-9]+]], 0x7fff
-; GCN: v_med3_i32 [[A]], 0xffff8000, [[A]], [[C]]
+; GFX10: v_cvt_pk_i16_i32_e64 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
+; GFX10: v_mov_b32_e32 [[C:v[0-9]+]], 0x7fff
+; GFX10: v_med3_i32 [[A]], 0xffff8000, [[A]], [[C]]
define i16 @v_clamp_i64_i16(i64 %in) nounwind {
entry:
%0 = icmp sgt i64 %in, -32768
@@ -22,15 +22,15 @@ entry:
ret i16 %4
}
-; GCN-LABEL: {{^}}v_clamp_i64_i16_reverse
+; GFX10-LABEL: {{^}}v_clamp_i64_i16_reverse
; GFX678: v_cvt_pk_i16_i32_e32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
; GFX9: v_cvt_pk_i16_i32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
; GFX6789: v_mov_b32_e32 [[B]], 0xffff8000
; GFX6789: v_mov_b32_e32 [[C:v[0-9]+]], 0x7fff
; GFX6789: v_med3_i32 [[A]], [[B]], [[A]], [[C]]
-; GCN: v_cvt_pk_i16_i32_e64 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
-; GCN: v_mov_b32_e32 [[C:v[0-9]+]], 0x7fff
-; GCN: v_med3_i32 [[A]], 0xffff8000, [[A]], [[C]]
+; GFX10: v_cvt_pk_i16_i32_e64 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
+; GFX10: v_mov_b32_e32 [[C:v[0-9]+]], 0x7fff
+; GFX10: v_med3_i32 [[A]], 0xffff8000, [[A]], [[C]]
define i16 @v_clamp_i64_i16_reverse(i64 %in) nounwind {
entry:
%0 = icmp slt i64 %in, 32767
@@ -42,13 +42,13 @@ entry:
ret i16 %4
}
-; GCN-LABEL: {{^}}v_clamp_i64_i16_wrong_lower
+; GFX10-LABEL: {{^}}v_clamp_i64_i16_wrong_lower
; GFX6789: v_mov_b32_e32 [[B:v[0-9]+]], 0x8001
; GFX6789: v_cndmask_b32_e32 [[A:v[0-9]+]], [[B]], [[A]], vcc
; GFX6789: v_cndmask_b32_e32 [[C:v[0-9]+]], 0, [[C]], vcc
-; GCN: v_cndmask_b32_e32 [[A:v[0-9]+]], 0x8001, [[A]], vcc_lo
-; GCN: v_cndmask_b32_e32 [[B:v[0-9]+]], 0, [[B]], vcc_lo
+; GFX10: v_cndmask_b32_e32 [[A:v[0-9]+]], 0x8001, [[A]], vcc_lo
+; GFX10: v_cndmask_b32_e32 [[B:v[0-9]+]], 0, [[B]], vcc_lo
define i16 @v_clamp_i64_i16_wrong_lower(i64 %in) nounwind {
entry:
%0 = icmp slt i64 %in, 32769
@@ -60,11 +60,11 @@ entry:
ret i16 %4
}
-; GCN-LABEL: {{^}}v_clamp_i64_i16_wrong_lower_and_higher
+; GFX10-LABEL: {{^}}v_clamp_i64_i16_wrong_lower_and_higher
; GFX6789: v_mov_b32_e32 [[B:v[0-9]+]], 0x8000
; GFX6789: v_cndmask_b32_e32 [[A:v[0-9]+]], [[B]], [[A]], vcc
-; GCN: v_cndmask_b32_e32 [[A:v[0-9]+]], 0x8000, [[A]], vcc_lo
+; GFX10: v_cndmask_b32_e32 [[A:v[0-9]+]], 0x8000, [[A]], vcc_lo
define i16 @v_clamp_i64_i16_wrong_lower_and_higher(i64 %in) nounwind {
entry:
%0 = icmp sgt i64 %in, -32769
@@ -76,15 +76,15 @@ entry:
ret i16 %4
}
-; GCN-LABEL: {{^}}v_clamp_i64_i16_lower_than_short
+; GFX10-LABEL: {{^}}v_clamp_i64_i16_lower_than_short
; GFX678: v_cvt_pk_i16_i32_e32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
; GFX9: v_cvt_pk_i16_i32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
; GFX6789: v_mov_b32_e32 [[B]], 0xffffff01
; GFX6789: v_mov_b32_e32 [[C:v[0-9]+]], 0x100
; GFX6789: v_med3_i32 [[A]], [[B]], [[A]], [[C]]
-; GCN: v_cvt_pk_i16_i32_e64 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
-; GCN: v_mov_b32_e32 [[C:v[0-9]+]], 0x100
-; GCN: v_med3_i32 [[A]], 0xffffff01, [[A]], [[C]]
+; GFX10: v_cvt_pk_i16_i32_e64 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
+; GFX10: v_mov_b32_e32 [[C:v[0-9]+]], 0x100
+; GFX10: v_med3_i32 [[A]], 0xffffff01, [[A]], [[C]]
define i16 @v_clamp_i64_i16_lower_than_short(i64 %in) nounwind {
entry:
%0 = icmp slt i64 %in, 256
@@ -96,15 +96,15 @@ entry:
ret i16 %4
}
-; GCN-LABEL: {{^}}v_clamp_i64_i16_lower_than_short_reverse
+; GFX10-LABEL: {{^}}v_clamp_i64_i16_lower_than_short_reverse
; GFX678: v_cvt_pk_i16_i32_e32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
; GFX9: v_cvt_pk_i16_i32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
; GFX6789: v_mov_b32_e32 [[B]], 0xffffff01
; GFX6789: v_mov_b32_e32 [[C:v[0-9]+]], 0x100
; GFX6789: v_med3_i32 [[A]], [[B]], [[A]], [[C]]
-; GCN: v_cvt_pk_i16_i32_e64 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
-; GCN: v_mov_b32_e32 [[C:v[0-9]+]], 0x100
-; GCN: v_med3_i32 [[A]], 0xffffff01, [[A]], [[C]]
+; GFX10: v_cvt_pk_i16_i32_e64 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
+; GFX10: v_mov_b32_e32 [[C:v[0-9]+]], 0x100
+; GFX10: v_med3_i32 [[A]], 0xffffff01, [[A]], [[C]]
define i16 @v_clamp_i64_i16_lower_than_short_reverse(i64 %in) nounwind {
entry:
%0 = icmp sgt i64 %in, -255
@@ -116,9 +116,9 @@ entry:
ret i16 %4
}
-; GCN-LABEL: {{^}}v_clamp_i64_i16_zero
+; GFX10-LABEL: {{^}}v_clamp_i64_i16_zero
; GFX678: v_mov_b32_e32 [[A:v[0-9]+]], 0
-; GCN: v_mov_b32_e32 [[A:v[0-9]+]], 0
+; GFX10: v_mov_b32_e32 [[A:v[0-9]+]], 0
define i16 @v_clamp_i64_i16_zero(i64 %in) nounwind {
entry:
%0 = icmp sgt i64 %in, 0
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