[llvm] ec04396 - clang-format
Thomas Symalla via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 2 00:15:57 PST 2021
Author: Thomas Symalla
Date: 2021-02-02T09:14:52+01:00
New Revision: ec043967ecb4bbfbf3bcbdad4055e9ba8e5dc21b
URL: https://github.com/llvm/llvm-project/commit/ec043967ecb4bbfbf3bcbdad4055e9ba8e5dc21b
DIFF: https://github.com/llvm/llvm-project/commit/ec043967ecb4bbfbf3bcbdad4055e9ba8e5dc21b.diff
LOG: clang-format
Added:
Modified:
llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h b/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
index badaafd2a57d..12a1d3854e37 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
@@ -469,11 +469,10 @@ m_GInsertVecElt(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2) {
}
template <typename Src0Ty, typename Src1Ty, typename Src2Ty>
-inline TernaryOp_match<Src0Ty, Src1Ty, Src2Ty,
- TargetOpcode::G_SELECT>
+inline TernaryOp_match<Src0Ty, Src1Ty, Src2Ty, TargetOpcode::G_SELECT>
m_GISelect(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2) {
- return TernaryOp_match<Src0Ty, Src1Ty, Src2Ty,
- TargetOpcode::G_SELECT>(Src0, Src1, Src2);
+ return TernaryOp_match<Src0Ty, Src1Ty, Src2Ty, TargetOpcode::G_SELECT>(
+ Src0, Src1, Src2);
}
/// Matches a register negated by a G_SUB.
@@ -497,8 +496,7 @@ m_Not(const SrcTy &&Src) {
// cmp sgt OR select (pred, x, value1) -> cmp sgt -> select (pred, origin,
// value2) -> cmp slt
// also binds the boundary values and the origin.
-template <typename Boundary1,
- typename Boundary2, typename Origin>
+template <typename Boundary1, typename Boundary2, typename Origin>
struct MaxMin_match_helper {
Boundary1 B1;
Boundary2 B2;
@@ -518,10 +516,14 @@ struct MaxMin_match_helper {
m_Reg(Base), B1))) {
CmpInst::Predicate Predicate2;
- if (mi_match(Base, MRI, m_GISelect(m_GICmp(m_Pred(Predicate2), m_Reg(), m_Reg()), O, B2))) {
- if ((Predicate1 == CmpInst::ICMP_SLT && Predicate2 == CmpInst::ICMP_SGT) ||
- (Predicate1 == CmpInst::ICMP_SGT && Predicate2 == CmpInst::ICMP_SLT)) {
- return true;
+ if (mi_match(Base, MRI,
+ m_GISelect(m_GICmp(m_Pred(Predicate2), m_Reg(), m_Reg()), O,
+ B2))) {
+ if ((Predicate1 == CmpInst::ICMP_SLT &&
+ Predicate2 == CmpInst::ICMP_SGT) ||
+ (Predicate1 == CmpInst::ICMP_SGT &&
+ Predicate2 == CmpInst::ICMP_SLT)) {
+ return true;
}
}
}
@@ -536,7 +538,7 @@ m_MaxMin(const Boundary1 &B1, const Boundary2 &B2, const Origin &O) {
return MaxMin_match_helper<Boundary1, Boundary2, Origin>(B1, B2, O);
}
-} // namespace GMIPatternMatch
+} // namespace MIPatternMatch
} // namespace llvm
#endif
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
index f6056c1584bc..03375a4c89bd 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
@@ -1,4 +1,5 @@
-//=== lib/CodeGen/GlobalISel/AMDGPUPostLegalizerCombiner.cpp ---------------===//
+//=== lib/CodeGen/GlobalISel/AMDGPUPostLegalizerCombiner.cpp
+//---------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -11,9 +12,14 @@
//
//===----------------------------------------------------------------------===//
+<<<<<<< HEAD
#include "AMDGPU.h"
#include "AMDGPULegalizerInfo.h"
#include "GCNSubtarget.h"
+=======
+#include "AMDGPULegalizerInfo.h"
+#include "AMDGPUTargetMachine.h"
+>>>>>>> clang-format
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "llvm/CodeGen/GlobalISel/Combiner.h"
#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
@@ -22,7 +28,11 @@
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/TargetPassConfig.h"
+<<<<<<< HEAD
#include "llvm/Target/TargetMachine.h"
+=======
+#include "llvm/Support/Debug.h"
+>>>>>>> clang-format
#define DEBUG_TYPE "amdgpu-postlegalizer-combiner"
@@ -74,8 +84,8 @@ class AMDGPUPostLegalizerCombinerHelper {
};
bool matchClampI64ToI16(MachineInstr &MI, MachineRegisterInfo &MRI,
- MachineFunction &MF,
- ClampI64ToI16MatchInfo &MatchInfo);
+ MachineFunction &MF,
+ ClampI64ToI16MatchInfo &MatchInfo);
void applyClampI64ToI16(MachineInstr &MI,
const ClampI64ToI16MatchInfo &MatchInfo);
@@ -201,11 +211,11 @@ void AMDGPUPostLegalizerCombinerHelper::applyUCharToFloat(MachineInstr &MI) {
SrcReg = B.buildAnyExtOrTrunc(S32, SrcReg).getReg(0);
if (Ty == S32) {
- B.buildInstr(AMDGPU::G_AMDGPU_CVT_F32_UBYTE0, {DstReg},
- {SrcReg}, MI.getFlags());
+ B.buildInstr(AMDGPU::G_AMDGPU_CVT_F32_UBYTE0, {DstReg}, {SrcReg},
+ MI.getFlags());
} else {
- auto Cvt0 = B.buildInstr(AMDGPU::G_AMDGPU_CVT_F32_UBYTE0, {S32},
- {SrcReg}, MI.getFlags());
+ auto Cvt0 = B.buildInstr(AMDGPU::G_AMDGPU_CVT_F32_UBYTE0, {S32}, {SrcReg},
+ MI.getFlags());
B.buildFPTrunc(DstReg, Cvt0, MI.getFlags());
}
@@ -258,9 +268,9 @@ void AMDGPUPostLegalizerCombinerHelper::applyCvtF32UByteN(
MI.eraseFromParent();
}
-bool AMDGPUPostLegalizerCombinerHelper::matchClampI64ToI16(MachineInstr &MI, MachineRegisterInfo &MRI,
- MachineFunction &MF,
- ClampI64ToI16MatchInfo &MatchInfo) {
+bool AMDGPUPostLegalizerCombinerHelper::matchClampI64ToI16(
+ MachineInstr &MI, MachineRegisterInfo &MRI, MachineFunction &MF,
+ ClampI64ToI16MatchInfo &MatchInfo) {
assert(MI.getOpcode() == TargetOpcode::G_TRUNC && "Invalid instruction!");
const LLT SrcType = MRI.getType(MI.getOperand(1).getReg());
if (SrcType != LLT::scalar(64))
@@ -271,14 +281,15 @@ bool AMDGPUPostLegalizerCombinerHelper::matchClampI64ToI16(MachineInstr &MI, Mac
LLVM_DEBUG(dbgs() << "Matching Clamp i64 to i16");
if (mi_match(MI.getOperand(1).getReg(), MRI,
- m_MaxMin(m_ICst(MatchInfo.Cmp1),
- m_ICst(MatchInfo.Cmp2),
+ m_MaxMin(m_ICst(MatchInfo.Cmp1), m_ICst(MatchInfo.Cmp2),
m_Reg(MatchInfo.Origin)))) {
const auto Cmp1 = static_cast<int64_t>(MatchInfo.Cmp1);
const auto Cmp2 = static_cast<int64_t>(MatchInfo.Cmp2);
- const int64_t Min = static_cast<int64_t>(std::numeric_limits<int16_t>::min());
- const int64_t Max = static_cast<int64_t>(std::numeric_limits<int16_t>::max());
+ const int64_t Min =
+ static_cast<int64_t>(std::numeric_limits<int16_t>::min());
+ const int64_t Max =
+ static_cast<int64_t>(std::numeric_limits<int16_t>::max());
// are we really trying to clamp against short boundaries?
return ((Cmp2 >= Cmp1 && Cmp1 >= Min && Cmp2 <= Max) ||
@@ -288,8 +299,8 @@ bool AMDGPUPostLegalizerCombinerHelper::matchClampI64ToI16(MachineInstr &MI, Mac
return false;
}
-void AMDGPUPostLegalizerCombinerHelper::applyClampI64ToI16(MachineInstr &MI,
- const ClampI64ToI16MatchInfo &MatchInfo) {
+void AMDGPUPostLegalizerCombinerHelper::applyClampI64ToI16(
+ MachineInstr &MI, const ClampI64ToI16MatchInfo &MatchInfo) {
LLVM_DEBUG(dbgs() << "Combining MI");
MachineIRBuilder B(MI);
@@ -429,6 +440,7 @@ class AMDGPUPostLegalizerCombiner : public MachineFunctionPass {
bool runOnMachineFunction(MachineFunction &MF) override;
void getAnalysisUsage(AnalysisUsage &AU) const override;
+
private:
bool IsOptNone;
};
@@ -448,7 +460,7 @@ void AMDGPUPostLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
}
AMDGPUPostLegalizerCombiner::AMDGPUPostLegalizerCombiner(bool IsOptNone)
- : MachineFunctionPass(ID), IsOptNone(IsOptNone) {
+ : MachineFunctionPass(ID), IsOptNone(IsOptNone) {
initializeAMDGPUPostLegalizerCombinerPass(*PassRegistry::getPassRegistry());
}
@@ -462,8 +474,8 @@ bool AMDGPUPostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
MF.getTarget().getOptLevel() != CodeGenOpt::None && !skipFunction(F);
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
- const AMDGPULegalizerInfo *LI
- = static_cast<const AMDGPULegalizerInfo *>(ST.getLegalizerInfo());
+ const AMDGPULegalizerInfo *LI =
+ static_cast<const AMDGPULegalizerInfo *>(ST.getLegalizerInfo());
GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
MachineDominatorTree *MDT =
@@ -476,8 +488,8 @@ bool AMDGPUPostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
char AMDGPUPostLegalizerCombiner::ID = 0;
INITIALIZE_PASS_BEGIN(AMDGPUPostLegalizerCombiner, DEBUG_TYPE,
- "Combine AMDGPU machine instrs after legalization",
- false, false)
+ "Combine AMDGPU machine instrs after legalization", false,
+ false)
INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
INITIALIZE_PASS_DEPENDENCY(GISelKnownBitsAnalysis)
INITIALIZE_PASS_END(AMDGPUPostLegalizerCombiner, DEBUG_TYPE,
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