[PATCH] D95804: [ARM] MVE vector lane interleaving

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: SjoerdMeijer, simon_tatham, efriedma, NickGuy, samtebbs, ostannard.
Herald added subscribers: danielkiss, nikic, hiraditya, kristof.beyls, mgorny.
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MVE does not have a single sext/zext or trunc instruction that takes the bottom half of a vector and extends to a full width, like NEON has with MOVL. Instead it is expected that this happens through top/bottom instructions. So the MVE equivalent VMOVLT/B instructions take either the even or odd elements of the input and extend them to the larger type, producing a vector with half the number of elements each of double the bitwidth. As there is no simple instruction, we often have to expand sext/zext/trunc into a series of lane moves (or stack loads/stores, which we do not do yet).

This pass takes vector code that starts at truncs, looks for interconnected blobs of operations that end with sext/zext and transforms them by adding shuffles so that the lanes are interleaved and the MVE VMOVL/VMOVN instructions can be used. This is done pre-ISel so that it can work across basic blocks.

This initial version of the pass just handles a limited set of instructions, not handling constants or splats or FP, which can all come as extensions to this base.


https://reviews.llvm.org/D95804

Files:
  llvm/lib/Target/ARM/ARM.h
  llvm/lib/Target/ARM/ARMTargetMachine.cpp
  llvm/lib/Target/ARM/CMakeLists.txt
  llvm/lib/Target/ARM/MVELaneInterleavingPass.cpp
  llvm/test/CodeGen/ARM/O3-pipeline.ll
  llvm/test/CodeGen/Thumb2/mve-laneinterleaving-cost.ll
  llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll

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