[llvm] 6a3ab66 - [RISCV] Update comment text from D95774. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2021-02-01T09:52:43-08:00
New Revision: 6a3ab66625cf1d440e66d9f438f05ee5ed040672

URL: https://github.com/llvm/llvm-project/commit/6a3ab66625cf1d440e66d9f438f05ee5ed040672
DIFF: https://github.com/llvm/llvm-project/commit/6a3ab66625cf1d440e66d9f438f05ee5ed040672.diff

LOG: [RISCV] Update comment text from D95774. NFC

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 9e6b11698d44a..3b65a87cd5845 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -553,10 +553,9 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
   }
   case ISD::SRL: {
     // Optimize (srl (and X, 0xffff), C) -> (srli (slli X, 16), 16 + C).
-    // Taking into account that the 0xffff may have had lower bits removed by
-    // SimplifyDemandedBits.
-    // This avoids materializing the 0xffff immediate. This pattern occurs when
-    // type legalizing i16 right shifts.
+    // Taking into account that the 0xffff may have had lower bits unset by
+    // SimplifyDemandedBits. This avoids materializing the 0xffff immediate.
+    // This pattern occurs when type legalizing i16 right shifts.
     // FIXME: This could be extended to other AND masks.
     auto *N1C = dyn_cast<ConstantSDNode>(Node->getOperand(1));
     if (N1C) {