[PATCH] D95774: [RISCV] Optimize (srl (and X, 0xffff), C) -> (srli (slli X, 16), 16 + C).

Luís Marques via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Feb 1 03:03:54 PST 2021


luismarques accepted this revision.
luismarques added a comment.
This revision is now accepted and ready to land.
Herald added a subscriber: StephenFan.

LGTM. Nice set of optimization patches!



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Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:556-557
+    // Optimize (srl (and X, 0xffff), C) -> (srli (slli X, 16), 16 + C).
+    // Taking into account that the 0xffff may have had lower bits removed by
+    // SimplifyDemandedBits.
+    // This avoids materializing the 0xffff immediate. This pattern occurs when
----------------
Nit: maybe "set to zero" instead of "removed", otherwise it seems like the mask was shifted?


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https://reviews.llvm.org/D95774



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