[llvm] 77f077b - [TableGen] Don't commute isel patterns if it would put an immAllOnesV or immAllZerosV on the left hand side.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2021-01-31T21:18:21-08:00
New Revision: 77f077b8c3b2e8bbf9b160d56194312e506dfe8f

URL: https://github.com/llvm/llvm-project/commit/77f077b8c3b2e8bbf9b160d56194312e506dfe8f
DIFF: https://github.com/llvm/llvm-project/commit/77f077b8c3b2e8bbf9b160d56194312e506dfe8f.diff

LOG: [TableGen] Don't commute isel patterns if it would put an immAllOnesV or immAllZerosV on the left hand side.

This primarily occurs with isel patterns using vnot. This reduces
the number of variants in the isel tables.

We generally canonicalize build_vectors of constants to the RHS. I think
we might fail if there is a bitcast on the build_vector, but that
should be easy to fix if we can find a case. Usually the
bitcast is introduced by type legalization or lowering. It's
likely canonicalization would have already occured.

Added: 
    

Modified: 
    llvm/utils/TableGen/CodeGenDAGPatterns.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/utils/TableGen/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
index 52c47f5e514b..01a6335a1632 100644
--- a/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
@@ -2637,6 +2637,8 @@ static bool OnlyOnRHSOfCommutative(TreePatternNode *N) {
     return true;
   if (N->isLeaf() && isa<IntInit>(N->getLeafValue()))
     return true;
+  if (isImmAllOnesAllZerosMatch(N))
+    return true;
   return false;
 }