[llvm] 1801e2a - RegAlloc: Fix assert if all registers in class reserved

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2021-01-31T11:10:04-05:00
New Revision: 1801e2aa249497adb5b0ab33e7fc5dd0ad4a4ab3

URL: https://github.com/llvm/llvm-project/commit/1801e2aa249497adb5b0ab33e7fc5dd0ad4a4ab3
DIFF: https://github.com/llvm/llvm-project/commit/1801e2aa249497adb5b0ab33e7fc5dd0ad4a4ab3.diff

LOG: RegAlloc: Fix assert if all registers in class reserved

With a context instruction, this would produce a context
error. However, it would continue on and do an out of bounds access of
the empty allocation order array.

Added: 
    llvm/test/CodeGen/AMDGPU/alloc-all-regs-reserved-in-class.mir

Modified: 
    llvm/lib/CodeGen/RegAllocBase.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/RegAllocBase.cpp b/llvm/lib/CodeGen/RegAllocBase.cpp
index aa749ca43e74..39787f246bea 100644
--- a/llvm/lib/CodeGen/RegAllocBase.cpp
+++ b/llvm/lib/CodeGen/RegAllocBase.cpp
@@ -124,7 +124,12 @@ void RegAllocBase::allocatePhysRegs() {
         if (MI->isInlineAsm())
           break;
       }
-      if (MI && MI->isInlineAsm()) {
+
+      const TargetRegisterClass *RC = MRI->getRegClass(VirtReg->reg());
+      ArrayRef<MCPhysReg> AllocOrder = RegClassInfo.getOrder(RC);
+      if (AllocOrder.empty())
+        report_fatal_error("no registers from class available to allocate");
+      else if (MI && MI->isInlineAsm()) {
         MI->emitError("inline assembly requires more registers than available");
       } else if (MI) {
         LLVMContext &Context =
@@ -133,10 +138,9 @@ void RegAllocBase::allocatePhysRegs() {
       } else {
         report_fatal_error("ran out of registers during register allocation");
       }
+
       // Keep going after reporting the error.
-      VRM->assignVirt2Phys(
-          VirtReg->reg(),
-          RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg())).front());
+      VRM->assignVirt2Phys(VirtReg->reg(), AllocOrder.front());
       continue;
     }
 

diff  --git a/llvm/test/CodeGen/AMDGPU/alloc-all-regs-reserved-in-class.mir b/llvm/test/CodeGen/AMDGPU/alloc-all-regs-reserved-in-class.mir
new file mode 100644
index 000000000000..f1308a1608c5
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/alloc-all-regs-reserved-in-class.mir
@@ -0,0 +1,18 @@
+# RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=greedy -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s
+
+# Check that there isn't an assert if we try to allocate a virtual register from
+# a class where all registers are reserved. All AGPRs are reserved on subtargets
+# that do not have them.
+
+# CHECK-NOT: ran out of registers during register allocation
+# CHECK: LLVM ERROR: no registers from class available to allocate
+# CHECK-NOT: ran out of registers during register allocation
+
+---
+name: use_agpr
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    %0:agpr_32 = IMPLICIT_DEF
+    S_ENDPGM 0, implicit %0
+...