[PATCH] D95620: [RISCV] Support scalable-vector integer reduction intrinsics

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck marked 2 inline comments as done.
frasercrmck added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:436
+      setOperationAction(ISD::VECREDUCE_ADD, VT, Custom);
+      setOperationAction(ISD::VECREDUCE_MUL, VT, Custom);
+      setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
----------------
HsiangKai wrote:
> You list ISD::VECREDUCE_MUL here, but you did not handle ISD::VECREDUCE_MUL in LowerOperation.
Thanks for spotting that. Copy/paste mistake.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95620/new/

https://reviews.llvm.org/D95620