[PATCH] D95699: [GlobalISel] Disable vector types in narrowScalarAddSub

[Cassie Jones via Phabricator via llvm-commits]

porglezomp updated this revision to Diff 320279.
porglezomp added a comment.

Use a temporary variable for the destination register/type


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95699/new/

https://reviews.llvm.org/D95699

Files:
  llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp


Index: llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
===================================================================
--- llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -4447,7 +4447,13 @@
   if (TypeIdx != 0)
     return UnableToLegalize;
 
-  uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
+  Register DstReg = MI.getOperand(0).getReg();
+  LLT DstType = MRI.getType(DstReg);
+  // FIXME: add support for vector types
+  if (DstType.isVector())
+    return UnableToLegalize;
+
+  uint64_t SizeOp0 = DstType.getSizeInBits();
   uint64_t NarrowSize = NarrowTy.getSizeInBits();
 
   // FIXME: add support for when SizeOp0 isn't an exact multiple of
@@ -4492,11 +4498,7 @@
     DstRegs.push_back(DstReg);
     CarryIn = CarryOut;
   }
-  Register DstReg = MI.getOperand(0).getReg();
-  if (MRI.getType(DstReg).isVector())
-    MIRBuilder.buildBuildVector(DstReg, DstRegs);
-  else
-    MIRBuilder.buildMerge(DstReg, DstRegs);
+  MIRBuilder.buildMerge(DstReg, DstRegs);
   MI.eraseFromParent();
   return Legalized;
 }


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