[llvm] d6656c3 - [GlobalISel] Remove hint instructions in generic InstructionSelect code.

[Jessica Paquette via llvm-commits]

Author: Jessica Paquette
Date: 2021-01-29T11:20:07-08:00
New Revision: d6656c3b258ef2c40ad089dbb4bfcbb29fd47d9e

URL: https://github.com/llvm/llvm-project/commit/d6656c3b258ef2c40ad089dbb4bfcbb29fd47d9e
DIFF: https://github.com/llvm/llvm-project/commit/d6656c3b258ef2c40ad089dbb4bfcbb29fd47d9e.diff

LOG: [GlobalISel] Remove hint instructions in generic InstructionSelect code.

I think every target will want to remove these in the same way. Rather than
making them all implement the same code, let's just put this in
InstructionSelect.

Differential Revision: https://reviews.llvm.org/D95652

Added: 
    llvm/test/CodeGen/AArch64/GlobalISel/select-hint.mir

Modified: 
    llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp b/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
index 25fae5487187..2d884517f0b5 100644
--- a/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
@@ -133,6 +133,15 @@ bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
         continue;
       }
 
+      // Eliminate hints.
+      if (isPreISelGenericOptimizationHint(MI.getOpcode())) {
+        Register DstReg = MI.getOperand(0).getReg();
+        Register SrcReg = MI.getOperand(1).getReg();
+        MI.eraseFromParent();
+        MRI.replaceRegWith(DstReg, SrcReg);
+        continue;
+      }
+
       if (!ISel->select(MI)) {
         // FIXME: It would be nice to dump all inserted instructions.  It's
         // not obvious how, esp. considering select() can insert after MI.

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-hint.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-hint.mir
new file mode 100644
index 000000000000..76b68ea09387
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-hint.mir
@@ -0,0 +1,64 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple aarch64 -debugify-and-strip-all-safe -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+# Check that we remove G_ASSERT_ZEXT during selection.
+
+...
+---
+name:            assert_zext_gpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $w0, $w1
+
+    ; CHECK-LABEL: name: assert_zext_gpr
+    ; CHECK: liveins: $w0, $w1
+    ; CHECK: %copy:gpr32all = COPY $w0
+    ; CHECK: $w1 = COPY %copy
+    ; CHECK: RET_ReallyLR implicit $w1
+    %copy:gpr(s32) = COPY $w0
+    %copy_assert_zext:gpr(s32) = G_ASSERT_ZEXT %copy, 16
+    $w1 = COPY %copy_assert_zext(s32)
+    RET_ReallyLR implicit $w1
+
+...
+---
+name:            assert_zext_fpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $s0, $s1
+
+    ; CHECK-LABEL: name: assert_zext_fpr
+    ; CHECK: liveins: $s0, $s1
+    ; CHECK: %copy:fpr32 = COPY $s0
+    ; CHECK: $s1 = COPY %copy
+    ; CHECK: RET_ReallyLR implicit $s1
+    %copy:fpr(s32) = COPY $s0
+    %copy_assert_zext:fpr(s32) = G_ASSERT_ZEXT %copy, 16
+    $s1 = COPY %copy_assert_zext(s32)
+    RET_ReallyLR implicit $s1
+
+...
+---
+name:            assert_zext_in_between_cross_bank
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $s0, $w1
+
+    ; CHECK-LABEL: name: assert_zext_in_between_cross_bank
+    ; CHECK: liveins: $s0, $w1
+    ; CHECK: %copy:fpr32 = COPY $s0
+    ; CHECK: $w1 = COPY %copy
+    ; CHECK: RET_ReallyLR implicit $w1
+    %copy:fpr(s32) = COPY $s0
+    %copy_assert_zext:fpr(s32) = G_ASSERT_ZEXT %copy, 16
+    $w1 = COPY %copy_assert_zext(s32)
+    RET_ReallyLR implicit $w1