[PATCH] D95586: [ARM] permit PC as destination of LSL
Nick Desaulniers via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 29 10:38:04 PST 2021
nickdesaulniers updated this revision to Diff 320169.
nickdesaulniers added a comment.
- limit changes to just MOVs with register operand
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D95586/new/
https://reviews.llvm.org/D95586
Files:
llvm/lib/Target/ARM/ARMInstrInfo.td
llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
llvm/test/MC/ARM/lsl-zero-errors.s
llvm/test/MC/Disassembler/ARM/unpredictable-LSL-regform.txt
Index: llvm/test/MC/Disassembler/ARM/unpredictable-LSL-regform.txt
===================================================================
--- llvm/test/MC/Disassembler/ARM/unpredictable-LSL-regform.txt
+++ llvm/test/MC/Disassembler/ARM/unpredictable-LSL-regform.txt
@@ -9,5 +9,5 @@
# A8.6.89 LSL (register)
# if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
-# CHECK: warning: potentially undefined instruction encoding
+# CHECK: lsl pc, r2, r1
0x12 0xf1 0xa0 0xe1
Index: llvm/test/MC/ARM/lsl-zero-errors.s
===================================================================
--- llvm/test/MC/ARM/lsl-zero-errors.s
+++ llvm/test/MC/ARM/lsl-zero-errors.s
@@ -153,3 +153,8 @@
// CHECK-ARM: movs sp, sp @ encoding: [0x0d,0xd0,0xb0,0xe1]
// CHECK-ARM: movs r0, sp @ encoding: [0x0d,0x00,0xb0,0xe1]
// CHECK-ARM: movs sp, r0 @ encoding: [0x00,0xd0,0xb0,0xe1]
+
+ movs pc, r1, lsl r2
+
+// CHECK-ARM: lsls pc, r1, r2 @ encoding: [0x11,0xf2,0xb0,0xe1]
+// CHECK-THUMBV7: error: operand must be a register in range [r0, r12] or r14
Index: llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
===================================================================
--- llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
+++ llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
@@ -843,7 +843,7 @@
; CHECK-LABEL: name: test_lshr_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
- ; CHECK: [[MOVsr:%[0-9]+]]:gprnopc = MOVsr [[COPY]], [[COPY1]], 3, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: [[MOVsr:%[0-9]+]]:gpr = MOVsr [[COPY]], [[COPY1]], 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[MOVsr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
@@ -872,7 +872,7 @@
; CHECK-LABEL: name: test_ashr_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
- ; CHECK: [[MOVsr:%[0-9]+]]:gprnopc = MOVsr [[COPY]], [[COPY1]], 1, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: [[MOVsr:%[0-9]+]]:gpr = MOVsr [[COPY]], [[COPY1]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[MOVsr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
@@ -901,7 +901,7 @@
; CHECK-LABEL: name: test_shl_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
- ; CHECK: [[MOVsr:%[0-9]+]]:gprnopc = MOVsr [[COPY]], [[COPY1]], 2, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: [[MOVsr:%[0-9]+]]:gpr = MOVsr [[COPY]], [[COPY1]], 2, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[MOVsr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
Index: llvm/lib/Target/ARM/ARMInstrInfo.td
===================================================================
--- llvm/lib/Target/ARM/ARMInstrInfo.td
+++ llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -3579,10 +3579,10 @@
let Inst{15-12} = Rd;
}
-def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
+def MOVsr : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_reg:$src),
DPSoRegRegFrm, IIC_iMOVsr,
"mov", "\t$Rd, $src",
- [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
+ [(set GPR:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
Sched<[WriteALU]> {
bits<4> Rd;
bits<12> src;
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