[PATCH] D95681: [GlobalISel] Fix modifying a G_OR without notifying the observer
Jay Foad via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 29 07:12:14 PST 2021
foad created this revision.
Herald added subscribers: hiraditya, rovka.
foad requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.
Remove the call to setFlags in favour of creating the instruction with
the correct flags in the first place, so we don't have to explicitly
notify the observer.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D95681
Files:
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
Index: llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
===================================================================
--- llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -5479,31 +5479,27 @@
auto NotSignBitMask = MIRBuilder.buildConstant(
Src0Ty, APInt::getLowBitsSet(Src0Size, Src0Size - 1));
- auto And0 = MIRBuilder.buildAnd(Src0Ty, Src0, NotSignBitMask);
- MachineInstr *Or;
-
+ Register And0 = MIRBuilder.buildAnd(Src0Ty, Src0, NotSignBitMask).getReg(0);
+ Register And1;
if (Src0Ty == Src1Ty) {
- auto And1 = MIRBuilder.buildAnd(Src1Ty, Src1, SignBitMask);
- Or = MIRBuilder.buildOr(Dst, And0, And1);
+ And1 = MIRBuilder.buildAnd(Src1Ty, Src1, SignBitMask).getReg(0);
} else if (Src0Size > Src1Size) {
auto ShiftAmt = MIRBuilder.buildConstant(Src0Ty, Src0Size - Src1Size);
auto Zext = MIRBuilder.buildZExt(Src0Ty, Src1);
auto Shift = MIRBuilder.buildShl(Src0Ty, Zext, ShiftAmt);
- auto And1 = MIRBuilder.buildAnd(Src0Ty, Shift, SignBitMask);
- Or = MIRBuilder.buildOr(Dst, And0, And1);
+ And1 = MIRBuilder.buildAnd(Src0Ty, Shift, SignBitMask).getReg(0);
} else {
auto ShiftAmt = MIRBuilder.buildConstant(Src1Ty, Src1Size - Src0Size);
auto Shift = MIRBuilder.buildLShr(Src1Ty, Src1, ShiftAmt);
auto Trunc = MIRBuilder.buildTrunc(Src0Ty, Shift);
- auto And1 = MIRBuilder.buildAnd(Src0Ty, Trunc, SignBitMask);
- Or = MIRBuilder.buildOr(Dst, And0, And1);
+ And1 = MIRBuilder.buildAnd(Src0Ty, Trunc, SignBitMask).getReg(0);
}
// Be careful about setting nsz/nnan/ninf on every instruction, since the
// constants are a nan and -0.0, but the final result should preserve
// everything.
- if (unsigned Flags = MI.getFlags())
- Or->setFlags(Flags);
+ unsigned Flags = MI.getFlags();
+ MIRBuilder.buildInstr(TargetOpcode::G_OR, {Dst}, {And0, And1}, Flags);
MI.eraseFromParent();
return Legalized;
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