[PATCH] D95677: [AArch64][SVE] Add unpredicated ld1/st1 patterns for reg+reg addressing modes

[Bradley Smith via Phabricator via llvm-commits]

bsmith created this revision.
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Add unpredicated ld1/st1 patterns for reg+reg addressing modes.

Additionally, avoid pulling calls to the vscale intrinsic out of a loop
in the IR LICM pass. This allows the reg+reg addressing mode patterns to
partially fold the call into the instruction during selection. MachineLICM will
take care of anything not folded.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D95677

Files:
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Transforms/Scalar/LICM.cpp
  llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-imm.ll
  llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll

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