[PATCH] D94579: [RISCV] add the MC layer support of P extension

[Jim Lin via Phabricator via llvm-commits]

Jim added a comment.

The registers used in most 'P' instruction should have v4i8 and v2i16 types for RV32 or v8i8 and v4i16 for RV64.



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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoP.td:430
+def BITREVI_32 : ALU_P_ri5<0b1110100, 0b000, "bitrevi">;
+def INSB_32    : ALU_P_ri2<0b1010110000, 0b000, "insb">;
+} // Predicates = [HasStdExtP, IsRV32]
----------------
The imm range for INSB_32 and INSB_64 is log of number of bytes (RV32 is 4, RV64 is 8).
It can be combined as one instruction.


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Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:183
 
+def GPRP : RegisterClass<"RISCV", [XLenVT], 32, (add
+    X10, X12, X14, X16,
----------------
It should combine (X10, X11), (X12, X13), .... together.
Not just represented as first register.



CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94579/new/

https://reviews.llvm.org/D94579