[PATCH] D95086: [DAGCombiner] Transform (zext (select c, load1, load2)) -> (select c, zextload1, zextload2)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: llvm/test/CodeGen/X86/select-ext.ll:71
   %ld2 = load volatile <2 x i32>, <2 x i32>* %arrayidx1
   %cond.v = select <2 x i1> %c, <2 x i32> %ld2, <2 x i32> %ld1
   %cond = zext <2 x i32> %cond.v to <2 x i64>
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Any chance we can support ISD::VSELECT as well?


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  https://reviews.llvm.org/D95086/new/

https://reviews.llvm.org/D95086