[PATCH] D95620: [RISCV] Support scalable-vector integer reduction intrinsics

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck created this revision.
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This patch adds support for the integer reduction intrinsics supported
by RVV. This excludes "mul" which has no corresponding instruction.

The reduction instructions in RVV have slightly complicated type
constraints given they always produce a single "M1 <https://reviews.llvm.org/M1>" vector register.
Since the scalar result is taken from the first element, it is
beneficial to use custom lowering so that the compiler understands the
sign bits of the result. This helps eliminate common sign-extensions
when the result type is less than XLEN.

The patch includes the second "scalar" reduction operand in the custom
nodes, even though they are always a zero-splat when lowering the
reduction intrinsics, in the hope that they can be useful for future DAG
combines.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D95620

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
  llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv64.ll

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