[PATCH] D95136: [X86] Fix tile config register spill issue.

Thu Jan 28 05:59:43 PST 2021

pengfei added inline comments.

================
Comment at: llvm/lib/Target/X86/X86PreTileConfig.cpp:297
+        for (auto I = MBB->pred_begin(), E = MBB->pred_end(); I != E; ++I) {
+          if (!BBVisitedInfo.count(*I))
+            continue;
----------------
LuoYuanke wrote:
> pengfei wrote:
> > LuoYuanke wrote:
> > > Not quite understand this. Isn't all BBs added at line 275?
> > No, we only added successors since ldtilecfg BB. BB0, BB1 and BB2 in below graph won't be added.
> > ```
> >     BB0   ldtilecfg
> >      |      / \
> >     BB1   BB4 BB5
> >     / \   /   /
> >   BB2  BB3  BB6
> >      \  |  /
> >        BB7
> > ```
> There is no AMX instruction in BB0, BB1, BB2, so we don't care about BB0, BB1, BB2?
Yes. BB ldtilecfg dominates all BB that have AMX. So, there's no AMX in BB0, BB1 and BB2. In fact, BB3 and BB7 don't have either.
We calculate the status here which are used by the BB in `BBUnsolved`, which will never use the status of BB0~2. Nevertheless, we know their stutus are always `NoAMXAtAll`.

Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95136/new/

https://reviews.llvm.org/D95136