[llvm] aa76ceb - Fix "32-bit shift result used in 64-bit comparison" MSVC warning. NFCI.

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2021-01-28T11:21:36Z
New Revision: aa76cebab59e7ae016a96215b1567b71489a4730

URL: https://github.com/llvm/llvm-project/commit/aa76cebab59e7ae016a96215b1567b71489a4730
DIFF: https://github.com/llvm/llvm-project/commit/aa76cebab59e7ae016a96215b1567b71489a4730.diff

LOG: Fix "32-bit shift result used in 64-bit comparison" MSVC warning. NFCI.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 0f5c41527c12..dd4bf517b47c 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -826,7 +826,7 @@ bool RISCVDAGToDAGISel::SelectAddrFI(SDValue Addr, SDValue &Base) {
 // from PatFrags in tablegen.
 bool RISCVDAGToDAGISel::isUnneededShiftMask(SDNode *N, unsigned Width) const {
   assert(N->getOpcode() == ISD::AND && "Unexpected opcode");
-  assert(Width >= 5 && N->getValueSizeInBits(0) >= (1 << Width) &&
+  assert(Width >= 5 && N->getValueSizeInBits(0) >= (1ULL << Width) &&
          "Unexpected width");
   const APInt &Val = N->getConstantOperandAPInt(1);