[llvm] f890fd5 - [llvm] Use llvm::is_sorted (NFC)
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 27 23:26:12 PST 2021
Author: Kazu Hirata
Date: 2021-01-27T23:25:39-08:00
New Revision: f890fd5f9130e67aae43f3bfd00c8530cdd6edc7
URL: https://github.com/llvm/llvm-project/commit/f890fd5f9130e67aae43f3bfd00c8530cdd6edc7
DIFF: https://github.com/llvm/llvm-project/commit/f890fd5f9130e67aae43f3bfd00c8530cdd6edc7.diff
LOG: [llvm] Use llvm::is_sorted (NFC)
Added:
Modified:
llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
llvm/lib/Target/X86/X86FloatingPoint.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
index 630490f6f914..0bb595b21107 100644
--- a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -297,12 +297,11 @@ char ARMConstantIslands::ID = 0;
void ARMConstantIslands::verify() {
#ifndef NDEBUG
BBInfoVector &BBInfo = BBUtils->getBBInfo();
- assert(std::is_sorted(MF->begin(), MF->end(),
- [&BBInfo](const MachineBasicBlock &LHS,
+ assert(is_sorted(*MF, [&BBInfo](const MachineBasicBlock &LHS,
const MachineBasicBlock &RHS) {
- return BBInfo[LHS.getNumber()].postOffset() <
- BBInfo[RHS.getNumber()].postOffset();
- }));
+ return BBInfo[LHS.getNumber()].postOffset() <
+ BBInfo[RHS.getNumber()].postOffset();
+ }));
LLVM_DEBUG(dbgs() << "Verifying " << CPUsers.size() << " CP users.\n");
for (unsigned i = 0, e = CPUsers.size(); i != e; ++i) {
CPUser &U = CPUsers[i];
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
index 744d919f2fd4..464fd01b56ae 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
@@ -807,11 +807,11 @@ void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI,
raw_ostream &O) {
if (MI->getOpcode() != ARM::t2CLRM) {
- assert(std::is_sorted(MI->begin() + OpNum, MI->end(),
- [&](const MCOperand &LHS, const MCOperand &RHS) {
- return MRI.getEncodingValue(LHS.getReg()) <
- MRI.getEncodingValue(RHS.getReg());
- }));
+ assert(is_sorted(drop_begin(*MI, OpNum),
+ [&](const MCOperand &LHS, const MCOperand &RHS) {
+ return MRI.getEncodingValue(LHS.getReg()) <
+ MRI.getEncodingValue(RHS.getReg());
+ }));
}
O << "{";
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
index 1cb99534f146..6df3af10fdcf 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
@@ -1730,11 +1730,11 @@ getRegisterListOpValue(const MCInst &MI, unsigned Op,
Binary |= NumRegs * 2;
} else {
const MCRegisterInfo &MRI = *CTX.getRegisterInfo();
- assert(std::is_sorted(MI.begin() + Op, MI.end(),
- [&](const MCOperand &LHS, const MCOperand &RHS) {
- return MRI.getEncodingValue(LHS.getReg()) <
+ assert(is_sorted(drop_begin(MI, Op),
+ [&](const MCOperand &LHS, const MCOperand &RHS) {
+ return MRI.getEncodingValue(LHS.getReg()) <
MRI.getEncodingValue(RHS.getReg());
- }));
+ }));
for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
unsigned RegNo = MRI.getEncodingValue(MI.getOperand(I).getReg());
Binary |= 1 << RegNo;
diff --git a/llvm/lib/Target/X86/X86FloatingPoint.cpp b/llvm/lib/Target/X86/X86FloatingPoint.cpp
index e6ee46957500..b0f2f23f8548 100644
--- a/llvm/lib/Target/X86/X86FloatingPoint.cpp
+++ b/llvm/lib/Target/X86/X86FloatingPoint.cpp
@@ -610,7 +610,7 @@ static int Lookup(ArrayRef<TableEntry> Table, unsigned Opcode) {
{ \
static std::atomic<bool> TABLE##Checked(false); \
if (!TABLE##Checked.load(std::memory_order_relaxed)) { \
- assert(std::is_sorted(std::begin(TABLE), std::end(TABLE)) && \
+ assert(is_sorted(TABLE) && \
"All lookup tables must be sorted for efficient access!"); \
TABLE##Checked.store(true, std::memory_order_relaxed); \
} \
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