[PATCH] D95136: [X86] Fix tile config register spill issue.

[Xiang Zhang via Phabricator via llvm-commits]

xiangzhangllvm added inline comments.


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Comment at: llvm/lib/Target/X86/X86PreTileConfig.cpp:283
+    // But iterating all BBs isn't too expensive here.
+    for (auto I : BBVisitedInfo) {
+      if (I.second.NeedUpdatePred)
----------------
I am not sure the order of iterate  BBVisitedInfo is right.
In map it may use "<" to sort its elements.


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Comment at: llvm/lib/Target/X86/X86PreTileConfig.cpp:292
+        if (BBVisitedInfo[MBB].LastAMX)
+          S = HasBeforeCallAMX;
+        if (BBVisitedInfo[MBB].HasCallBeforeAMX)
----------------
What does HasBeforeCallAMX really mean, why set it once BB has AMX ?


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Comment at: llvm/lib/Target/X86/X86PreTileConfig.cpp:298
+          if (!BBVisitedInfo.count(*I))
+            continue;
+          if (S > BBVisitedInfo[*I].MaxSucc) {
----------------
Not sure directly continue is right, if the status required by the visited predecessors.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95136/new/

https://reviews.llvm.org/D95136