[PATCH] D95086: [DAGCombiner] Transform (zext (select c, load1, load2)) -> (select c, zextload1, zextload2)

[Guozhi Wei via Phabricator via llvm-commits]

Carrot added inline comments.


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Comment at: llvm/test/CodeGen/X86/select-ext.ll:20
 }
 
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Carrot wrote:
> RKSimon wrote:
> > Worth adding sextload test case? What about vectors?
> Never thought about vector cases. Will look into it.
The current patch can also handle vectors. In the new test case, sext_vector is compiled to following without this patch

```
sext_vector:                            # @sext_vector
        .cfi_startproc
# %bb.0:
        movq    (%rdi), %xmm1                   # xmm1 = mem[0],zero
        movq    8(%rdi), %xmm0                  # xmm0 = mem[0],zero
        testl   %esi, %esi
        jne     .LBB3_2
# %bb.1:
        movdqa  %xmm1, %xmm0
.LBB3_2:
        pmovsxdq        %xmm0, %xmm0
        retq

With this patch I got

sext_vector:                            # @sext_vector
        .cfi_startproc
# %bb.0:
        pmovsxdq        (%rdi), %xmm1
        pmovsxdq        8(%rdi), %xmm0
        testl   %esi, %esi
        jne     .LBB3_2
# %bb.1:
        movdqa  %xmm1, %xmm0
.LBB3_2:
        retq
```

The sign extension instruction before return is removed.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95086/new/

https://reviews.llvm.org/D95086