[PATCH] D95565: [GlobalISel] Add hint elimination combine
Jessica Paquette via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 27 14:36:03 PST 2021
paquette created this revision.
paquette added reviewers: aemerson, arsenm.
Herald added subscribers: hiraditya, rovka.
paquette requested review of this revision.
Herald added a subscriber: wdng.
Herald added a project: LLVM.
This adds a hint elimination combine, which changes
%x = ...
%y = G_ASSERT_ZEXT %x, n
...
%z = G_FOO ... %y ...
into
%x = ...
...
%z = G_FOO ... %x
This is intended to run in a late combiner, post-legalization.
https://reviews.llvm.org/D95565
Files:
llvm/include/llvm/Target/GlobalISel/Combine.td
llvm/lib/Target/AArch64/AArch64Combine.td
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-hint.mir
Index: llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-hint.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-hint.mir
@@ -0,0 +1,22 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64 -run-pass=aarch64-postlegalizer-lowering -verify-machineinstrs %s -o - | FileCheck %s
+#
+# Check that we remove hint instructions.
+
+---
+name: assert_zext
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $w0, $w1
+ ; CHECK-LABEL: name: assert_zext
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK: %copy:_(s32) = COPY $w1
+ ; CHECK: $w0 = COPY %copy(s32)
+ ; CHECK: RET_ReallyLR implicit $w0
+ %copy:_(s32) = COPY $w1
+ %hint:_(s32) = G_ASSERT_ZEXT %copy, 16
+ $w0 = COPY %hint
+ RET_ReallyLR implicit $w0
+...
Index: llvm/lib/Target/AArch64/AArch64Combine.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64Combine.td
+++ llvm/lib/Target/AArch64/AArch64Combine.td
@@ -125,7 +125,7 @@
def AArch64PostLegalizerLoweringHelper
: GICombinerHelper<"AArch64GenPostLegalizerLoweringHelper",
[shuffle_vector_pseudos, vashr_vlshr_imm,
- icmp_lowering, form_duplane]> {
+ icmp_lowering, form_duplane, eliminate_hints]> {
let DisableRuleOption = "aarch64postlegalizerlowering-disable-rule";
}
Index: llvm/include/llvm/Target/GlobalISel/Combine.td
===================================================================
--- llvm/include/llvm/Target/GlobalISel/Combine.td
+++ llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -557,6 +557,21 @@
def insert_vec_elt_combines : GICombineGroup<
[combine_insert_vec_elts_build_vector]>;
+// Remove hint instructions in the same way as copies.
+//
+// %x = ...
+// %y = G_ASSERT_ZEXT %x, n
+// ... = G_FOO %y, ...
+// ->
+//
+// %x = ...
+// ... G_FOO %x, ...
+def eliminate_hints: GICombineRule<
+ (defs root:$root),
+ (match (wip_match_opcode G_ASSERT_ZEXT):$root,
+ [{ return true; }]),
+ (apply [{ Helper.applyCombineCopy(*${root}); }])>;
+
// FIXME: These should use the custom predicate feature once it lands.
def undef_combines : GICombineGroup<[undef_to_fp_zero, undef_to_int_zero,
undef_to_negative_one,
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