[PATCH] D95563: [RISCV] Add initial support for 128-bit fixed vectors with RVV.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: frasercrmck, HsiangKai, rogfer01, evandro.
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This adds basic support for 128-bit fixed vectors using a single vector
register as the 1.0 V spec has a minimum VLEN of 128 bits. This
first patch includes support for VV versions of the integer and FP
binary operations and vector loads and stores. This is all off by
default and requires a command line to enable.

Portions of this are inspired by the D91638 <https://reviews.llvm.org/D91638> proof of concept from
Fraser Cormack.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D95563

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll

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