[PATCH] D95381: [ARM] Select VINS from vector inserts

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


================
Comment at: llvm/lib/Target/ARM/ARMInstrVFP.td:1129
 def VINSH  : ASuInp<0b11101, 0b11, 0b0000, 0b11, 0,
-                  (outs SPR:$Sd), (ins SPR:$Sm),
+                  (outs SPR:$Sd), (ins SPR:$Sda, SPR:$Sm),
                   IIC_fpUNA16, "vins.f16\t$Sd, $Sm", []>,
----------------
SjoerdMeijer wrote:
> SjoerdMeijer wrote:
> > dmgreen wrote:
> > > SjoerdMeijer wrote:
> > > > It's unclear to me why we need 2 inputs to model that it is inserting into the top half of an existing register. I forgot if this is how that's done, is there precedent for this?
> > > It's similar to how most things work, yeah. Things like VMOVHcc work like that, or any of the MVE vp.inactive where you conditionally move lanes of the input into the output. The VMOVN also have an input for Qd_src and an output for Qd, combining the two into a single value.
> > > 
> > > We are taking some of the value from Sda (the bottom half) and some from Sm (the top half), combining them into a single value.
> > > We are taking some of the value from Sda (the bottom half) and some from Sm (the top half), combining them into a single value.
> > 
> > Okay, but should the constraint then be:
> > 
> >   "$Sd = $Sm"
> > 
> > Sorry, I might be using you to relearn isel patterns....
> correction:
> 
>   "$Sda = $Sm"
I think it's good as-is - we want to make sure the Sd and Sda are the same register. The final instruction is then `VINS Sd, Sm`, and with Sda==Sd we are now inserting Sm into the top half of Sda, to produce Sd.


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  https://reviews.llvm.org/D95381/new/

https://reviews.llvm.org/D95381