[PATCH] D94615: [RISCV] Add RVV insertelt/extractelt scalable-vector patterns

[Craig Topper via Phabricator via llvm-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM with that comment fix.



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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2311
     // The number of sign bits of the scalar result is computed by obtaining the
     // element type of the input vector operand, substracting its width from the
+    // XLEN, and then adding one (sign bit within the element type). If the
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While you're here, can you fix substracting->subtracting


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94615/new/

https://reviews.llvm.org/D94615