[PATCH] D95379: [ARM] [ELF] Fix ARMMaterializeGV for Indirect calls

[Adhemerval Zanella via Phabricator via llvm-commits]

zatrazz created this revision.
zatrazz added reviewers: ostannard, kristof.beyls, MaskRay.
Herald added subscribers: danielkiss, hiraditya.
zatrazz requested review of this revision.
Herald added a project: LLVM.

Recent shouldAssumeDSOLocal changes (introduced by 961f31d8ad14c66 <https://reviews.llvm.org/rG961f31d8ad14c66829991522d73e14b5a96ff6d4>)
do not take in consideration the relocation model anymore.  The ARM
fast-isel pass uses the function return to set whether a global symbol
is loaded indirectly or not, and without the expected information
llvm now generates an extra load for following code:

$ cat test.ll
@__asan_option_detect_stack_use_after_return = external global i32
define dso_local i32 @main(i32 %argc, i8** %argv) #0 {
entry:

  %0 = load i32, i32* @__asan_option_detect_stack_use_after_return,

align 4

  %1 = icmp ne i32 %0, 0
  br i1 %1, label %2, label %3

2:

  ret i32 0

3:

  ret i32 1

}

attributes #0 = { noinline optnone }

$ lcc test.ll -o -
[...]
main:

  .fnstart

[...]

  movw    r0, :lower16:__asan_option_detect_stack_use_after_return
  movt    r0, :upper16:__asan_option_detect_stack_use_after_return
  ldr     r0, [r0]
  ldr     r0, [r0]
  cmp     r0, #0

[...]

And without 'optnone' it produces:
[...]
main:

  .fnstart

[...]

  movw    r0, :lower16:__asan_option_detect_stack_use_after_return
  movt    r0, :upper16:__asan_option_detect_stack_use_after_return
  ldr     r0, [r0]
  clz     r0, r0
  lsr     r0, r0, #5
  bx      lr

[...]

This triggered a lot of invalid memory access in sanitizers for
arm-linux-gnueabihf.  I checked this patch both a stage1 built with
gcc and a stage2 bootstrap and it fixes all the Linux sanitizers
issues.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D95379

Files:
  llvm/lib/Target/ARM/ARMFastISel.cpp
  llvm/test/CodeGen/ARM/fast-isel-intrinsic.ll


Index: llvm/test/CodeGen/ARM/fast-isel-intrinsic.ll
===================================================================
--- llvm/test/CodeGen/ARM/fast-isel-intrinsic.ll
+++ llvm/test/CodeGen/ARM/fast-isel-intrinsic.ll
@@ -61,8 +61,8 @@
 
 ; ARM-ELF: movw [[REG1:r[0-9]+]], :lower16:temp
 ; ARM-ELF: movt [[REG1]], :upper16:temp
-; ARM-ELF:      add [[REG1]], r1, #4
-; ARM-ELF-NEXT: add r1, r1, #16
+; ARM-ELF:      add r0, [[REG1]], #4
+; ARM-ELF-NEXT: add r1, [[REG1]], #16
 
 ; ARM: movw r2, #17
 ; ARM: bl {{_?}}memcpy
@@ -106,7 +106,7 @@
 
 ; ARM-ELF: movw [[REG0:r[0-9]+]], :lower16:temp
 ; ARM-ELF: movt [[REG0]], :upper16:temp
-; ARM-ELF:      add [[REG0]], r1, #4
+; ARM-ELF:      add r0, [[REG0]], #4
 ; ARM-ELF-NEXT: add r1, r1, #16
 
 ; ARM: movw r2, #10
Index: llvm/lib/Target/ARM/ARMFastISel.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMFastISel.cpp
+++ llvm/lib/Target/ARM/ARMFastISel.cpp
@@ -606,7 +606,9 @@
     }
   }
 
-  if (IsIndirect) {
+  if ((Subtarget->isTargetELF() && Subtarget->isGVInGOT(GV)) ||
+      (Subtarget->isTargetMachO() && IsIndirect) ||
+      Subtarget->genLongCalls()) {
     MachineInstrBuilder MIB;
     unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
     if (isThumb2)


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