[PATCH] D95285: [RISCV] Use sign extend for i32 arguments and returns in makeLibCall on RV64.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 25 09:34:29 PST 2021
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG4eb4f8963f1e: [RISCV] Use sign extend for i32 arguments and returns in makeLibCall on RV64. (authored by craig.topper).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D95285/new/
https://reviews.llvm.org/D95285
Files:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll
Index: llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll
+++ llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll
@@ -80,7 +80,6 @@
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __ltsf2 at plt
-; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: slti a0, a0, 0
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
@@ -96,7 +95,6 @@
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __lesf2 at plt
-; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: slti a0, a0, 1
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
@@ -112,7 +110,6 @@
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __gtsf2 at plt
-; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: sgtz a0, a0
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
@@ -128,7 +125,6 @@
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __gesf2 at plt
-; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: addi a1, zero, -1
; RV64I-NEXT: slt a0, a1, a0
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@@ -214,8 +210,7 @@
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: srli a0, a0, 32
+; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: call __floatunsisf at plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
@@ -675,8 +670,7 @@
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a1, a1, 32
-; RV64I-NEXT: srli a1, a1, 32
+; RV64I-NEXT: sext.w a1, a1
; RV64I-NEXT: call __powisf2 at plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Index: llvm/lib/Target/RISCV/RISCVISelLowering.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -217,6 +217,7 @@
getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
bool shouldExtendTypeInLibCall(EVT Type) const override;
+ bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
/// Returns the register with the specified architectural or ABI name. This
/// method is necessary to lower the llvm.read_register.* and
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -4250,6 +4250,13 @@
return true;
}
+bool RISCVTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
+ if (Subtarget.is64Bit() && Type == MVT::i32)
+ return true;
+
+ return IsSigned;
+}
+
bool RISCVTargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT,
SDValue C) const {
// Check integral scalar types.
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