[PATCH] D95361: [ARM][RegisterScavenging] Don't consider LR liveout if it is not reloaded

[Tomas Matheson via Phabricator via llvm-commits]

tmatheson created this revision.
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https://bugs.llvm.org/show_bug.cgi?id=48232

When PrologEpilogInserter writes callee-saved registers to the stack, LR is not reloaded but is instead loaded directly into PC.
This was not taken into account when determining if each callee-saved register was liveout for the block.
When frame elimination inserts virtual registers, and the register scavenger tries to scavenge LR, it considers it liveout and tries to spill again.
However there is no emergency spill slot to use, and it fails with an error:

  fatal error: error in backend: Error while trying to spill LR from class GPR: Cannot scavenge register without an emergency spill slot!

This patch pervents any callee-saved registers which are not reloaded (including LR) from being marked liveout.
They are therefore available to scavenge without requiring an extra spill.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D95361

Files:
  llvm/lib/CodeGen/LiveRegUnits.cpp
  llvm/test/CodeGen/AArch64/scavenge-lr.mir
  llvm/test/CodeGen/Thumb2/mve-multivec-spill.ll

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