[llvm] 12d0753 - [RISCV] Use bitsLE instead of strict == MVT::i32 in assertsexti32 and assertzexti32.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Jan 24 14:01:38 PST 2021
Author: Craig Topper
Date: 2021-01-24T13:58:14-08:00
New Revision: 12d0753aca22896fda2cf76781b0ee0524d55065
URL: https://github.com/llvm/llvm-project/commit/12d0753aca22896fda2cf76781b0ee0524d55065
DIFF: https://github.com/llvm/llvm-project/commit/12d0753aca22896fda2cf76781b0ee0524d55065.diff
LOG: [RISCV] Use bitsLE instead of strict == MVT::i32 in assertsexti32 and assertzexti32.
The patterns that use this really want to know if the operand has at
least 32 sign/zero bits.
This increases opportunities to use W instructions when the original
source used i8/i16. Not sure how much this matters for performance,
but it makes i8/i16 code more consistent with i32.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/test/CodeGen/RISCV/double-convert.ll
llvm/test/CodeGen/RISCV/float-convert.ll
llvm/test/CodeGen/RISCV/half-convert.ll
llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index c03a406972a5..1b5683ab64cb 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -838,13 +838,13 @@ def IsOrAdd: PatFrag<(ops node:$A, node:$B), (or node:$A, node:$B), [{
return isOrEquivalentToAdd(N);
}]>;
def assertsexti32 : PatFrag<(ops node:$src), (assertsext node:$src), [{
- return cast<VTSDNode>(N->getOperand(1))->getVT() == MVT::i32;
+ return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLE(MVT::i32);
}]>;
def sexti32 : PatFrags<(ops node:$src),
[(sext_inreg node:$src, i32),
(assertsexti32 node:$src)]>;
def assertzexti32 : PatFrag<(ops node:$src), (assertzext node:$src), [{
- return cast<VTSDNode>(N->getOperand(1))->getVT() == MVT::i32;
+ return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLE(MVT::i32);
}]>;
def zexti32 : PatFrags<(ops node:$src),
[(and node:$src, 0xffffffff),
diff --git a/llvm/test/CodeGen/RISCV/double-convert.ll b/llvm/test/CodeGen/RISCV/double-convert.ll
index 5599775ffd68..a2e53a5a48d2 100644
--- a/llvm/test/CodeGen/RISCV/double-convert.ll
+++ b/llvm/test/CodeGen/RISCV/double-convert.ll
@@ -281,7 +281,7 @@ define double @fcvt_d_w_i8(i8 signext %a) nounwind {
;
; RV64IFD-LABEL: fcvt_d_w_i8:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.d.l ft0, a0
+; RV64IFD-NEXT: fcvt.d.w ft0, a0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
%1 = sitofp i8 %a to double
@@ -301,7 +301,7 @@ define double @fcvt_d_wu_i8(i8 zeroext %a) nounwind {
;
; RV64IFD-LABEL: fcvt_d_wu_i8:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.d.lu ft0, a0
+; RV64IFD-NEXT: fcvt.d.wu ft0, a0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
%1 = uitofp i8 %a to double
@@ -321,7 +321,7 @@ define double @fcvt_d_w_i16(i16 signext %a) nounwind {
;
; RV64IFD-LABEL: fcvt_d_w_i16:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.d.l ft0, a0
+; RV64IFD-NEXT: fcvt.d.w ft0, a0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
%1 = sitofp i16 %a to double
@@ -341,7 +341,7 @@ define double @fcvt_d_wu_i16(i16 zeroext %a) nounwind {
;
; RV64IFD-LABEL: fcvt_d_wu_i16:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.d.lu ft0, a0
+; RV64IFD-NEXT: fcvt.d.wu ft0, a0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
%1 = uitofp i16 %a to double
diff --git a/llvm/test/CodeGen/RISCV/float-convert.ll b/llvm/test/CodeGen/RISCV/float-convert.ll
index de4be78f3cf6..bf9f576b68f0 100644
--- a/llvm/test/CodeGen/RISCV/float-convert.ll
+++ b/llvm/test/CodeGen/RISCV/float-convert.ll
@@ -202,7 +202,7 @@ define float @fcvt_s_w_i8(i8 signext %a) nounwind {
;
; RV64IF-LABEL: fcvt_s_w_i8:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.l ft0, a0
+; RV64IF-NEXT: fcvt.s.w ft0, a0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
%1 = sitofp i8 %a to float
@@ -218,7 +218,7 @@ define float @fcvt_s_wu_i8(i8 zeroext %a) nounwind {
;
; RV64IF-LABEL: fcvt_s_wu_i8:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.lu ft0, a0
+; RV64IF-NEXT: fcvt.s.wu ft0, a0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
%1 = uitofp i8 %a to float
@@ -234,7 +234,7 @@ define float @fcvt_s_w_i16(i16 signext %a) nounwind {
;
; RV64IF-LABEL: fcvt_s_w_i16:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.l ft0, a0
+; RV64IF-NEXT: fcvt.s.w ft0, a0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
%1 = sitofp i16 %a to float
@@ -250,7 +250,7 @@ define float @fcvt_s_wu_i16(i16 zeroext %a) nounwind {
;
; RV64IF-LABEL: fcvt_s_wu_i16:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.lu ft0, a0
+; RV64IF-NEXT: fcvt.s.wu ft0, a0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
%1 = uitofp i16 %a to float
diff --git a/llvm/test/CodeGen/RISCV/half-convert.ll b/llvm/test/CodeGen/RISCV/half-convert.ll
index bc9122a7618e..30b5809ac8da 100644
--- a/llvm/test/CodeGen/RISCV/half-convert.ll
+++ b/llvm/test/CodeGen/RISCV/half-convert.ll
@@ -213,12 +213,12 @@ define half @fcvt_h_si_signext(i16 signext %a) nounwind {
;
; RV64IZFH-LABEL: fcvt_h_si_signext:
; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.h.l fa0, a0
+; RV64IZFH-NEXT: fcvt.h.w fa0, a0
; RV64IZFH-NEXT: ret
;
; RV64IDZFH-LABEL: fcvt_h_si_signext:
; RV64IDZFH: # %bb.0:
-; RV64IDZFH-NEXT: fcvt.h.l fa0, a0
+; RV64IDZFH-NEXT: fcvt.h.w fa0, a0
; RV64IDZFH-NEXT: ret
%1 = sitofp i16 %a to half
ret half %1
@@ -273,12 +273,12 @@ define half @fcvt_h_ui_zeroext(i16 zeroext %a) nounwind {
;
; RV64IZFH-LABEL: fcvt_h_ui_zeroext:
; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.h.lu fa0, a0
+; RV64IZFH-NEXT: fcvt.h.wu fa0, a0
; RV64IZFH-NEXT: ret
;
; RV64IDZFH-LABEL: fcvt_h_ui_zeroext:
; RV64IDZFH: # %bb.0:
-; RV64IDZFH-NEXT: fcvt.h.lu fa0, a0
+; RV64IDZFH-NEXT: fcvt.h.wu fa0, a0
; RV64IDZFH-NEXT: ret
%1 = uitofp i16 %a to half
ret half %1
diff --git a/llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll b/llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll
index a6d9e294f85e..2f13680933b3 100644
--- a/llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll
+++ b/llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll
@@ -1091,7 +1091,7 @@ define zeroext i32 @zext_remw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind
define signext i8 @sext_remw_sext_sext_i8(i8 signext %a, i8 signext %b) nounwind {
; RV64IM-LABEL: sext_remw_sext_sext_i8:
; RV64IM: # %bb.0:
-; RV64IM-NEXT: rem a0, a0, a1
+; RV64IM-NEXT: remw a0, a0, a1
; RV64IM-NEXT: slli a0, a0, 56
; RV64IM-NEXT: srai a0, a0, 56
; RV64IM-NEXT: ret
@@ -1102,7 +1102,7 @@ define signext i8 @sext_remw_sext_sext_i8(i8 signext %a, i8 signext %b) nounwind
define signext i16 @sext_remw_sext_sext_i16(i16 signext %a, i16 signext %b) nounwind {
; RV64IM-LABEL: sext_remw_sext_sext_i16:
; RV64IM: # %bb.0:
-; RV64IM-NEXT: rem a0, a0, a1
+; RV64IM-NEXT: remw a0, a0, a1
; RV64IM-NEXT: slli a0, a0, 48
; RV64IM-NEXT: srai a0, a0, 48
; RV64IM-NEXT: ret
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