[PATCH] D95289: [TargetLowering][RISCV] Don't turn (seteq/ne (sext_inreg X, VT), C1) -> (seteq/ne (zext_inreg X, VT), C1) if the sext_inreg is cheaper

[Craig Topper via Phabricator via llvm-commits]

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RISCV has to use 2 shifts for (i64 (zext_inreg X, i32)), but we
can use addiw rd, rs1, x0 for sext_inreg. We already understood this
when type legalizing i32 seteq/ne on rv64. But this transform in
SimplifySetCC would sometimes undo it.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D95289

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
  llvm/test/CodeGen/RISCV/setcc-logic.ll
  llvm/test/CodeGen/RISCV/sext-zext-trunc.ll

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