[PATCH] D95136: [X86] Fix tile config register spill issue.

[Pengfei Wang via Phabricator via llvm-commits]

pengfei marked 2 inline comments as done.
pengfei added inline comments.


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Comment at: llvm/lib/Target/X86/X86PreTileConfig.cpp:242
+      LastAMX = &*I;
+      LastAMXSet.erase(CPP.first);
+    } else if (I->isCall()) {
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LuoYuanke wrote:
> This is not clear to me. In below example, do we only insert tilerelease in amx1? Does call2 have chance to be iterated? We may add more test cases for different scenario.
>                      call0
>                   /        \
>               amx1       amx2
>                 call1       call2
The previous code doesn't have these problem. Anyway, I changed the algorithm. It should be more clear now. Could you have a new review?


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  https://reviews.llvm.org/D95136/new/

https://reviews.llvm.org/D95136