[PATCH] D95214: [RISCV]A bug when llc -O0 vfmv.f.s.ll

Fri Jan 22 19:30:42 PST 2021

craig.topper added a comment.

In D95214#2517296 <https://reviews.llvm.org/D95214#2517296>, @StephenFan wrote:

> In D95214#2517277 <https://reviews.llvm.org/D95214#2517277>, @craig.topper wrote:
>
>> @StephenFan  thank you for the bug report. I had a feeling that converting FPR32 to FPR64 with a SUBREG_TO_REG could cause a problem.
>
> I have a question that why not make the scalar float point as FPR64 (not FPR32) then when encounter the FPR32  or FPR16, use the EXTRACT_SUBREG opcode.

If you look at the current output for the fpr-spill-scalar.ll test added in D95234 <https://reviews.llvm.org/D95234>, you'll see that we would generate a 8 byte spill slot for float and half if we use FPR64. But the instruction to store an 8 byte F register isn't supported without the D extension.

In D95214#2517296 <https://reviews.llvm.org/D95214#2517296>, @StephenFan wrote:

> In D95214#2517277 <https://reviews.llvm.org/D95214#2517277>, @craig.topper wrote:
>
>> @StephenFan  thank you for the bug report. I had a feeling that converting FPR32 to FPR64 with a SUBREG_TO_REG could cause a problem.
>
> I have a question that why not make the scalar float point as FPR64 (not FPR32) then when encounter the FPR32  or FPR16, use the EXTRACT_SUBREG opcode.

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https://reviews.llvm.org/D95214