[PATCH] D95136: [X86] Fix tile config register spill issue.

[LuoYuanke via Phabricator via llvm-commits]

LuoYuanke added inline comments.


================
Comment at: llvm/lib/Target/X86/X86PreTileConfig.cpp:242
+      LastAMX = &*I;
+      LastAMXSet.erase(CPP.first);
+    } else if (I->isCall()) {
----------------
This is not clear to me. In below example, do we only insert tilerelease in amx1? Does call2 have chance to be iterated? We may add more test cases for different scenario.
                     call0
                  /        \
              amx1       amx2
                call1       call2


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95136/new/

https://reviews.llvm.org/D95136