[PATCH] D95275: [AArch64][GlobalISel] Fix instruction selection for G_USUBO

[Cassie Jones via Phabricator via llvm-commits]

porglezomp created this revision.
porglezomp added reviewers: hctim, aemerson, paquette.
Herald added subscribers: danielkiss, hiraditya, kristof.beyls, rovka.
porglezomp requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

G_USUBO needs to be checked for overflow with the LO condition code
instead of the HS condition code.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D95275

Files:
  llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/select-usubo.mir


Index: llvm/test/CodeGen/AArch64/GlobalISel/select-usubo.mir
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/select-usubo.mir
+++ llvm/test/CodeGen/AArch64/GlobalISel/select-usubo.mir
@@ -17,7 +17,7 @@
     ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
     ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
     ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
-    ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
+    ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
     ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[CSINCWr]], 0, 0
     ; CHECK: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[UBFMWri]], 0, 7
     ; CHECK: $w0 = COPY [[UBFMWri1]]
@@ -46,7 +46,7 @@
     ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
     ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
     ; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
-    ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
+    ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
     ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[CSINCWr]], 0, 0
     ; CHECK: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[UBFMWri]], 0, 7
     ; CHECK: $w0 = COPY [[UBFMWri1]]
@@ -75,7 +75,7 @@
     ; CHECK: liveins: $w0, $w1, $x2
     ; CHECK: %copy:gpr32sp = COPY $w0
     ; CHECK: %add:gpr32 = SUBSWri %copy, 16, 0, implicit-def $nzcv
-    ; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
+    ; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
     ; CHECK: $w0 = COPY %add
     ; CHECK: RET_ReallyLR implicit $w0
     %copy:gpr(s32) = COPY $w0
@@ -101,7 +101,7 @@
     ; CHECK: %copy1:gpr32 = COPY $w0
     ; CHECK: %copy2:gpr32 = COPY $w1
     ; CHECK: %add:gpr32 = SUBSWrs %copy1, %copy2, 16, implicit-def $nzcv
-    ; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
+    ; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
     ; CHECK: $w0 = COPY %add
     ; CHECK: RET_ReallyLR implicit $w0
     %copy1:gpr(s32) = COPY $w0
@@ -128,7 +128,7 @@
     ; CHECK: liveins: $w0, $w1, $x2
     ; CHECK: %copy:gpr32sp = COPY $w0
     ; CHECK: %add:gpr32 = ADDSWri %copy, 16, 0, implicit-def $nzcv
-    ; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
+    ; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
     ; CHECK: $w0 = COPY %add
     ; CHECK: RET_ReallyLR implicit $w0
     %copy:gpr(s32) = COPY $w0
@@ -153,7 +153,7 @@
     ; CHECK: %reg0:gpr64sp = COPY $x0
     ; CHECK: %reg1:gpr32 = COPY $w0
     ; CHECK: %add:gpr64 = SUBSXrx %reg0, %reg1, 18, implicit-def $nzcv
-    ; CHECK: %flags:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
+    ; CHECK: %flags:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
     ; CHECK: $x0 = COPY %add
     ; CHECK: RET_ReallyLR implicit $x0
     %reg0:gpr(s64) = COPY $x0
Index: llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
===================================================================
--- llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -4377,7 +4377,7 @@
   case TargetOpcode::G_SSUBO:
     return std::make_pair(emitSUBS(Dst, LHS, RHS, MIRBuilder), AArch64CC::VS);
   case TargetOpcode::G_USUBO:
-    return std::make_pair(emitSUBS(Dst, LHS, RHS, MIRBuilder), AArch64CC::HS);
+    return std::make_pair(emitSUBS(Dst, LHS, RHS, MIRBuilder), AArch64CC::LO);
   }
 }
 


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