[llvm] 607e5a5 - [RISCV] Add B extension tests to make sure RV64 only instructions aren't accepted in RV32.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 22 13:52:45 PST 2021
Author: Craig Topper
Date: 2021-01-22T13:52:26-08:00
New Revision: 607e5a5000bddec24061b54a7e7955d51fe0d049
URL: https://github.com/llvm/llvm-project/commit/607e5a5000bddec24061b54a7e7955d51fe0d049
DIFF: https://github.com/llvm/llvm-project/commit/607e5a5000bddec24061b54a7e7955d51fe0d049.diff
LOG: [RISCV] Add B extension tests to make sure RV64 only instructions aren't accepted in RV32.
Add tests to make sure common instructions are accepted in RV64
and not just RV32.
Reviewed By: asb, frasercrmck
Differential Revision: https://reviews.llvm.org/D95150
Added:
llvm/test/MC/RISCV/rv64zbc-valid.s
Modified:
llvm/test/MC/RISCV/rv32zba-invalid.s
llvm/test/MC/RISCV/rv32zbb-invalid.s
llvm/test/MC/RISCV/rv32zbbp-invalid.s
llvm/test/MC/RISCV/rv32zbe-invalid.s
llvm/test/MC/RISCV/rv32zbf-invalid.s
llvm/test/MC/RISCV/rv32zbp-invalid.s
llvm/test/MC/RISCV/rv32zbproposedc-invalid.s
llvm/test/MC/RISCV/rv32zbr-invalid.s
llvm/test/MC/RISCV/rv32zbs-invalid.s
llvm/test/MC/RISCV/rv32zbt-invalid.s
llvm/test/MC/RISCV/rv64zba-valid.s
llvm/test/MC/RISCV/rv64zbb-valid.s
llvm/test/MC/RISCV/rv64zbbp-valid.s
llvm/test/MC/RISCV/rv64zbe-valid.s
llvm/test/MC/RISCV/rv64zbf-valid.s
llvm/test/MC/RISCV/rv64zbp-valid.s
llvm/test/MC/RISCV/rv64zbproposedc-valid.s
llvm/test/MC/RISCV/rv64zbr-valid.s
llvm/test/MC/RISCV/rv64zbs-valid.s
llvm/test/MC/RISCV/rv64zbt-valid.s
Removed:
################################################################################
diff --git a/llvm/test/MC/RISCV/rv32zba-invalid.s b/llvm/test/MC/RISCV/rv32zba-invalid.s
index 64adfe03fdfb..1005fab1b8ed 100644
--- a/llvm/test/MC/RISCV/rv32zba-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zba-invalid.s
@@ -6,3 +6,8 @@ sh1add t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
sh2add t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Too few operands
sh3add t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+slli.uw t0, t1, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+add.uw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+sh1add.uw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+sh2add.uw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+sh3add.uw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
diff --git a/llvm/test/MC/RISCV/rv32zbb-invalid.s b/llvm/test/MC/RISCV/rv32zbb-invalid.s
index 4e40b44ee02c..ea6a17032fef 100644
--- a/llvm/test/MC/RISCV/rv32zbb-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zbb-invalid.s
@@ -18,3 +18,6 @@ max t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
minu t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Too few operands
maxu t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+clzw t0, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+ctzw t0, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+cpopw t0, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
diff --git a/llvm/test/MC/RISCV/rv32zbbp-invalid.s b/llvm/test/MC/RISCV/rv32zbbp-invalid.s
index a8ba4a659498..286f6050434b 100644
--- a/llvm/test/MC/RISCV/rv32zbbp-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zbbp-invalid.s
@@ -15,3 +15,7 @@ rori t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Immediate operand out of range
rori t0, t1, 32 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31]
rori t0, t1, -1 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31]
+rolw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+rorw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+roriw t0, t1, 31 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+roriw t0, t1, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
diff --git a/llvm/test/MC/RISCV/rv32zbe-invalid.s b/llvm/test/MC/RISCV/rv32zbe-invalid.s
index 537154d3fc60..4d4124778f13 100644
--- a/llvm/test/MC/RISCV/rv32zbe-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zbe-invalid.s
@@ -4,3 +4,5 @@
bdecompress t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Too few operands
bcompress t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+bdecompressw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+bcompressw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
diff --git a/llvm/test/MC/RISCV/rv32zbf-invalid.s b/llvm/test/MC/RISCV/rv32zbf-invalid.s
index 61947618562e..c701e2559869 100644
--- a/llvm/test/MC/RISCV/rv32zbf-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zbf-invalid.s
@@ -2,3 +2,4 @@
# Too few operands
bfp t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+bfpw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
diff --git a/llvm/test/MC/RISCV/rv32zbp-invalid.s b/llvm/test/MC/RISCV/rv32zbp-invalid.s
index f5eac72b3b88..6de719a250dd 100644
--- a/llvm/test/MC/RISCV/rv32zbp-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zbp-invalid.s
@@ -54,3 +54,16 @@ xperm.n t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
xperm.b t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Too few operands
xperm.h t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+slow t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+srow t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+sloiw t0, t1, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+sroiw t0, t1, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+gorcw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+grevw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+gorciw t0, t1, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+greviw t0, t1, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+shflw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+unshflw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+packw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+packuw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+xperm.w t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
diff --git a/llvm/test/MC/RISCV/rv32zbproposedc-invalid.s b/llvm/test/MC/RISCV/rv32zbproposedc-invalid.s
index a1861b74af0b..942852a34b1e 100644
--- a/llvm/test/MC/RISCV/rv32zbproposedc-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zbproposedc-invalid.s
@@ -1,5 +1,6 @@
-# RUN: not llvm-mc -triple riscv32 -mattr=+c,+experimental-zbproposedc < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+c,+experimental-zbproposedc,+experimental-Zba < %s 2>&1 | FileCheck %s
# Too many operands
c.not s0, s1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
c.neg s0, s1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+c.zext.w s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
diff --git a/llvm/test/MC/RISCV/rv32zbr-invalid.s b/llvm/test/MC/RISCV/rv32zbr-invalid.s
index c25d7dd0c01b..9a6a6b5fbf40 100644
--- a/llvm/test/MC/RISCV/rv32zbr-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zbr-invalid.s
@@ -12,3 +12,5 @@ crc32c.b t0, t1, t2 # CHECK: :[[@LINE]]:18: error: invalid operand for instructi
crc32c.h t0, t1, t2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction
# Too many operands
crc32c.w t0, t1, t2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction
+crc32.d t0, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+crc32c.d t0, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
diff --git a/llvm/test/MC/RISCV/rv32zbs-invalid.s b/llvm/test/MC/RISCV/rv32zbs-invalid.s
index 90af46dc248b..74c0cda1beb0 100644
--- a/llvm/test/MC/RISCV/rv32zbs-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zbs-invalid.s
@@ -28,3 +28,10 @@ bexti t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Immediate operand out of range
bexti t0, t1, 32 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31]
bexti t0, t1, -1 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31]
+bclrw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+bsetw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+binvw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+bextw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+bclriw t0, t1, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+bsetiw t0, t1, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+binviw t0, t1, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
diff --git a/llvm/test/MC/RISCV/rv32zbt-invalid.s b/llvm/test/MC/RISCV/rv32zbt-invalid.s
index 1c41990984a0..2d81463572f7 100644
--- a/llvm/test/MC/RISCV/rv32zbt-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zbt-invalid.s
@@ -13,3 +13,6 @@ fsri t0, t1, t2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Immediate operand out of range
fsri t0, t1, t2, 32 # CHECK: :[[@LINE]]:18: error: immediate must be an integer in the range [0, 31]
fsri t0, t1, t2, -1 # CHECK: :[[@LINE]]:18: error: immediate must be an integer in the range [0, 31]
+fslw t0, t1, t2, t3 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+fsrw t0, t1, t2, t3 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+fsriw t0, t1, t2, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
diff --git a/llvm/test/MC/RISCV/rv64zba-valid.s b/llvm/test/MC/RISCV/rv64zba-valid.s
index 9cce642cb298..41d200254129 100644
--- a/llvm/test/MC/RISCV/rv64zba-valid.s
+++ b/llvm/test/MC/RISCV/rv64zba-valid.s
@@ -27,3 +27,12 @@ sh2add.uw t0, t1, t2
# CHECK-ASM-AND-OBJ: sh3add.uw t0, t1, t2
# CHECK-ASM: encoding: [0xbb,0x62,0x73,0x20]
sh3add.uw t0, t1, t2
+# CHECK-ASM-AND-OBJ: sh1add t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x22,0x73,0x20]
+sh1add t0, t1, t2
+# CHECK-ASM-AND-OBJ: sh2add t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x20]
+sh2add t0, t1, t2
+# CHECK-ASM-AND-OBJ: sh3add t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x20]
+sh3add t0, t1, t2
diff --git a/llvm/test/MC/RISCV/rv64zbb-valid.s b/llvm/test/MC/RISCV/rv64zbb-valid.s
index 9e4678573298..a67a8ab5a1df 100644
--- a/llvm/test/MC/RISCV/rv64zbb-valid.s
+++ b/llvm/test/MC/RISCV/rv64zbb-valid.s
@@ -12,6 +12,33 @@
# RUN: | llvm-objdump --mattr=+experimental-zbb -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# CHECK-ASM-AND-OBJ: clz t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x03,0x60]
+clz t0, t1
+# CHECK-ASM-AND-OBJ: ctz t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x13,0x60]
+ctz t0, t1
+# CHECK-ASM-AND-OBJ: cpop t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x23,0x60]
+cpop t0, t1
+# CHECK-ASM-AND-OBJ: sext.b t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x43,0x60]
+sext.b t0, t1
+# CHECK-ASM-AND-OBJ: sext.h t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x53,0x60]
+sext.h t0, t1
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+# CHECK-ASM-AND-OBJ: minu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x0a]
+minu t0, t1, t2
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+# CHECK-ASM-AND-OBJ: maxu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x72,0x73,0x0a]
+maxu t0, t1, t2
# CHECK-ASM-AND-OBJ: clzw t0, t1
# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x60]
clzw t0, t1
diff --git a/llvm/test/MC/RISCV/rv64zbbp-valid.s b/llvm/test/MC/RISCV/rv64zbbp-valid.s
index 9fbced2fd427..ace28e13fd61 100644
--- a/llvm/test/MC/RISCV/rv64zbbp-valid.s
+++ b/llvm/test/MC/RISCV/rv64zbbp-valid.s
@@ -19,6 +19,27 @@
# RUN: | llvm-objdump --mattr=+experimental-zbp -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# CHECK-ASM-AND-OBJ: andn t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x72,0x73,0x40]
+andn t0, t1, t2
+# CHECK-ASM-AND-OBJ: orn t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x40]
+orn t0, t1, t2
+# CHECK-ASM-AND-OBJ: xnor t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x40]
+xnor t0, t1, t2
+# CHECK-ASM-AND-OBJ: rol t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x60]
+rol t0, t1, t2
+# CHECK-ASM-AND-OBJ: ror t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x60]
+ror t0, t1, t2
+# CHECK-ASM-AND-OBJ: rori t0, t1, 31
+# CHECK-ASM: encoding: [0x93,0x52,0xf3,0x61]
+rori t0, t1, 31
+# CHECK-ASM-AND-OBJ: rori t0, t1, 0
+# CHECK-ASM: encoding: [0x93,0x52,0x03,0x60]
+rori t0, t1, 0
# CHECK-ASM-AND-OBJ: rolw t0, t1, t2
# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x60]
rolw t0, t1, t2
diff --git a/llvm/test/MC/RISCV/rv64zbc-valid.s b/llvm/test/MC/RISCV/rv64zbc-valid.s
new file mode 100644
index 000000000000..237b7403aad0
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64zbc-valid.s
@@ -0,0 +1,23 @@
+# With B extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
+# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# With Bitmanip carry-less multiply extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbc -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbc < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbc -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: clmul t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x0a]
+clmul t0, t1, t2
+# CHECK-ASM-AND-OBJ: clmulr t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x22,0x73,0x0a]
+clmulr t0, t1, t2
+# CHECK-ASM-AND-OBJ: clmulh t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x32,0x73,0x0a]
+clmulh t0, t1, t2
diff --git a/llvm/test/MC/RISCV/rv64zbe-valid.s b/llvm/test/MC/RISCV/rv64zbe-valid.s
index 6ebba3ea3990..e5ffbcb1a83f 100644
--- a/llvm/test/MC/RISCV/rv64zbe-valid.s
+++ b/llvm/test/MC/RISCV/rv64zbe-valid.s
@@ -12,6 +12,12 @@
# RUN: | llvm-objdump --mattr=+experimental-zbe -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# CHECK-ASM-AND-OBJ: bdecompress t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x48]
+bdecompress t0, t1, t2
+# CHECK-ASM-AND-OBJ: bcompress t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x08]
+bcompress t0, t1, t2
# CHECK-ASM-AND-OBJ: bdecompressw t0, t1, t2
# CHECK-ASM: encoding: [0xbb,0x62,0x73,0x48]
bdecompressw t0, t1, t2
diff --git a/llvm/test/MC/RISCV/rv64zbf-valid.s b/llvm/test/MC/RISCV/rv64zbf-valid.s
index 1a2a41a33d05..aec1957092e8 100644
--- a/llvm/test/MC/RISCV/rv64zbf-valid.s
+++ b/llvm/test/MC/RISCV/rv64zbf-valid.s
@@ -12,6 +12,9 @@
# RUN: | llvm-objdump --mattr=+experimental-zbf -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# CHECK-ASM-AND-OBJ: bfp t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x72,0x73,0x48]
+bfp t0, t1, t2
# CHECK-ASM-AND-OBJ: bfpw t0, t1, t2
# CHECK-ASM: encoding: [0xbb,0x72,0x73,0x48]
bfpw t0, t1, t2
diff --git a/llvm/test/MC/RISCV/rv64zbp-valid.s b/llvm/test/MC/RISCV/rv64zbp-valid.s
index 7fbc684b9c3d..8d7324eaabe0 100644
--- a/llvm/test/MC/RISCV/rv64zbp-valid.s
+++ b/llvm/test/MC/RISCV/rv64zbp-valid.s
@@ -12,6 +12,51 @@
# RUN: | llvm-objdump --mattr=+experimental-zbp -d -r - \
# RUN: | FileCheck --check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+# CHECK-ASM-AND-OBJ: slo t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x20]
+slo t0, t1, t2
+# CHECK-ASM-AND-OBJ: sro t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x20]
+sro t0, t1, t2
+# CHECK-ASM-AND-OBJ: sloi t0, t1, 0
+# CHECK-ASM: encoding: [0x93,0x12,0x03,0x20]
+sloi t0, t1, 0
+# CHECK-ASM-AND-OBJ: sroi t0, t1, 0
+# CHECK-ASM: encoding: [0x93,0x52,0x03,0x20]
+sroi t0, t1, 0
+# CHECK-ASM-AND-OBJ: gorc t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x28]
+gorc t0, t1, t2
+# CHECK-ASM-AND-OBJ: grev t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x68]
+grev t0, t1, t2
+# CHECK-ASM-AND-OBJ: gorci t0, t1, 0
+# CHECK-ASM: encoding: [0x93,0x52,0x03,0x28]
+gorci t0, t1, 0
+# CHECK-ASM-AND-OBJ: grevi t0, t1, 0
+# CHECK-ASM: encoding: [0x93,0x52,0x03,0x68]
+grevi t0, t1, 0
+# CHECK-ASM-AND-OBJ: shfl t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x08]
+shfl t0, t1, t2
+# CHECK-ASM-AND-OBJ: unshfl t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x08]
+unshfl t0, t1, t2
+# CHECK-ASM-AND-OBJ: shfli t0, t1, 0
+# CHECK-ASM: encoding: [0x93,0x12,0x03,0x08]
+shfli t0, t1, 0
+# CHECK-ASM-AND-OBJ: unshfli t0, t1, 0
+# CHECK-ASM: encoding: [0x93,0x52,0x03,0x08]
+unshfli t0, t1, 0
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+# CHECK-ASM-AND-OBJ: packh t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x72,0x73,0x08]
+packh t0, t1, t2
# CHECK-ASM-AND-OBJ: slow t0, t1, t2
# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x20]
slow t0, t1, t2
@@ -69,6 +114,15 @@ orc.b t0, t1
# CHECK-OBJ: orc.b t0, t1
# CHECK-ASM: encoding: [0x93,0x52,0x73,0x28]
gorci t0, t1, 7
+# CHECK-ASM-AND-OBJ: xperm.n t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x22,0x73,0x28]
+xperm.n t0, t1, t2
+# CHECK-ASM-AND-OBJ: xperm.b t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x28]
+xperm.b t0, t1, t2
+# CHECK-ASM-AND-OBJ: xperm.h t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x28
+xperm.h t0, t1, t2
# CHECK-ASM-AND-OBJ: xperm.w t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x02,0x73,0x28]
xperm.w t0, t1, t2
diff --git a/llvm/test/MC/RISCV/rv64zbproposedc-valid.s b/llvm/test/MC/RISCV/rv64zbproposedc-valid.s
index a30f3bb85479..ad161e4ee0a7 100644
--- a/llvm/test/MC/RISCV/rv64zbproposedc-valid.s
+++ b/llvm/test/MC/RISCV/rv64zbproposedc-valid.s
@@ -5,6 +5,12 @@
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# CHECK-ASM-AND-OBJ: c.not s0
+# CHECK-ASM: encoding: [0x01,0x60]
+c.not s0
+# CHECK-ASM-AND-OBJ: c.neg s0
+# CHECK-ASM: encoding: [0x01,0x64]
+c.neg s0
# CHECK-ASM-AND-OBJ: c.zext.w s0
# CHECK-ASM: encoding: [0x01,0x68]
c.zext.w s0
diff --git a/llvm/test/MC/RISCV/rv64zbr-valid.s b/llvm/test/MC/RISCV/rv64zbr-valid.s
index 15aa9006d5bf..f1ff120c9d83 100644
--- a/llvm/test/MC/RISCV/rv64zbr-valid.s
+++ b/llvm/test/MC/RISCV/rv64zbr-valid.s
@@ -12,6 +12,24 @@
# RUN: | llvm-objdump --mattr=+experimental-zbr -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# CHECK-ASM-AND-OBJ: crc32.b t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x03,0x61]
+crc32.b t0, t1
+# CHECK-ASM-AND-OBJ: crc32.h t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x13,0x61]
+crc32.h t0, t1
+# CHECK-ASM-AND-OBJ: crc32.w t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x23,0x61]
+crc32.w t0, t1
+# CHECK-ASM-AND-OBJ: crc32c.b t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x83,0x61]
+crc32c.b t0, t1
+# CHECK-ASM-AND-OBJ: crc32c.h t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x93,0x61]
+crc32c.h t0, t1
+# CHECK-ASM-AND-OBJ: crc32c.w t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0xa3,0x61]
+crc32c.w t0, t1
# CHECK-ASM-AND-OBJ: crc32.d t0, t1
# CHECK-ASM: encoding: [0x93,0x12,0x33,0x61]
crc32.d t0, t1
diff --git a/llvm/test/MC/RISCV/rv64zbs-valid.s b/llvm/test/MC/RISCV/rv64zbs-valid.s
index ed1fd0baa421..51a8902f65da 100644
--- a/llvm/test/MC/RISCV/rv64zbs-valid.s
+++ b/llvm/test/MC/RISCV/rv64zbs-valid.s
@@ -12,6 +12,30 @@
# RUN: | llvm-objdump --mattr=+experimental-zbs -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# CHECK-ASM-AND-OBJ: bclr t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x48]
+bclr t0, t1, t2
+# CHECK-ASM-AND-OBJ: bset t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x28]
+bset t0, t1, t2
+# CHECK-ASM-AND-OBJ: binv t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x68]
+binv t0, t1, t2
+# CHECK-ASM-AND-OBJ: bext t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x48]
+bext t0, t1, t2
+# CHECK-ASM-AND-OBJ: bclri t0, t1, 1
+# CHECK-ASM: encoding: [0x93,0x12,0x13,0x48]
+bclri t0, t1, 1
+# CHECK-ASM-AND-OBJ: bseti t0, t1, 1
+# CHECK-ASM: encoding: [0x93,0x12,0x13,0x28]
+bseti t0, t1, 1
+# CHECK-ASM-AND-OBJ: binvi t0, t1, 1
+# CHECK-ASM: encoding: [0x93,0x12,0x13,0x68]
+binvi t0, t1, 1
+# CHECK-ASM-AND-OBJ: bexti t0, t1, 1
+# CHECK-ASM: encoding: [0x93,0x52,0x13,0x48]
+bexti t0, t1, 1
# CHECK-ASM-AND-OBJ: bclrw t0, t1, t2
# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x48]
bclrw t0, t1, t2
diff --git a/llvm/test/MC/RISCV/rv64zbt-valid.s b/llvm/test/MC/RISCV/rv64zbt-valid.s
index 7db0c8d3dbb9..a0a7e48ccd29 100644
--- a/llvm/test/MC/RISCV/rv64zbt-valid.s
+++ b/llvm/test/MC/RISCV/rv64zbt-valid.s
@@ -12,6 +12,21 @@
# RUN: | llvm-objdump --mattr=+experimental-zbt -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
+# CHECK-ASM-AND-OBJ: cmov t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0xd2,0x63,0xe6]
+cmov t0, t1, t2, t3
+# CHECK-ASM-AND-OBJ: fsl t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x12,0xc3,0x3d]
+fsl t0, t1, t2, t3
+# CHECK-ASM-AND-OBJ: fsr t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x52,0xc3,0x3d]
+fsr t0, t1, t2, t3
+# CHECK-ASM-AND-OBJ: fsri t0, t1, t2, 0
+# CHECK-ASM: encoding: [0x93,0x52,0x03,0x3c]
+fsri t0, t1, t2, 0
# CHECK-ASM-AND-OBJ: fslw t0, t1, t2, t3
# CHECK-ASM: encoding: [0xbb,0x12,0xc3,0x3d]
fslw t0, t1, t2, t3
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