[PATCH] D94999: [RISCV] Add xperm.* instructions to Zbp extension.

[Craig Topper via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGf25f7e8ecd91: [RISCV] Add xperm.* instructions to Zbp extension. (authored by craig.topper).

Changed prior to commit:
  https://reviews.llvm.org/D94999?vs=318241&id=318625#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94999/new/

https://reviews.llvm.org/D94999

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/test/MC/RISCV/rv32zbp-invalid.s
  llvm/test/MC/RISCV/rv32zbp-valid.s
  llvm/test/MC/RISCV/rv64zbp-invalid.s
  llvm/test/MC/RISCV/rv64zbp-valid.s


Index: llvm/test/MC/RISCV/rv64zbp-valid.s
===================================================================
--- llvm/test/MC/RISCV/rv64zbp-valid.s
+++ llvm/test/MC/RISCV/rv64zbp-valid.s
@@ -69,3 +69,6 @@
 # CHECK-OBJ: orc.b t0, t1
 # CHECK-ASM: encoding: [0x93,0x52,0x73,0x28]
 gorci t0, t1, 7
+# CHECK-ASM-AND-OBJ: xperm.w t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x02,0x73,0x28]
+xperm.w t0, t1, t2
Index: llvm/test/MC/RISCV/rv64zbp-invalid.s
===================================================================
--- llvm/test/MC/RISCV/rv64zbp-invalid.s
+++ llvm/test/MC/RISCV/rv64zbp-invalid.s
@@ -32,3 +32,5 @@
 shflw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 unshflw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+xperm.w t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
Index: llvm/test/MC/RISCV/rv32zbp-valid.s
===================================================================
--- llvm/test/MC/RISCV/rv32zbp-valid.s
+++ llvm/test/MC/RISCV/rv32zbp-valid.s
@@ -78,3 +78,12 @@
 # CHECK-OBJ: orc.b t0, t1
 # CHECK-ASM: encoding: [0x93,0x52,0x73,0x28]
 gorci t0, t1, 7
+# CHECK-ASM-AND-OBJ: xperm.n t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x22,0x73,0x28]
+xperm.n t0, t1, t2
+# CHECK-ASM-AND-OBJ: xperm.b t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x28]
+xperm.b t0, t1, t2
+# CHECK-ASM-AND-OBJ: xperm.h t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x28
+xperm.h t0, t1, t2
Index: llvm/test/MC/RISCV/rv32zbp-invalid.s
===================================================================
--- llvm/test/MC/RISCV/rv32zbp-invalid.s
+++ llvm/test/MC/RISCV/rv32zbp-invalid.s
@@ -48,3 +48,9 @@
 packu t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 packh t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+xperm.n t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+xperm.b t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+xperm.h t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
Index: llvm/lib/Target/RISCV/RISCVInstrInfoB.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -252,6 +252,12 @@
 def GREV : ALU_rr<0b0110100, 0b101, "grev">, Sched<[]>;
 } // Predicates = [HasStdExtZbp]
 
+let Predicates = [HasStdExtZbp] in {
+def XPERMN : ALU_rr<0b0010100, 0b010, "xperm.n">, Sched<[]>;
+def XPERMB : ALU_rr<0b0010100, 0b100, "xperm.b">, Sched<[]>;
+def XPERMH : ALU_rr<0b0010100, 0b110, "xperm.h">, Sched<[]>;
+} // Predicates = [HasStdExtZbp]
+
 let Predicates = [HasStdExtZbp] in {
 def SLOI : RVBShift_ri<0b00100, 0b001, OPC_OP_IMM, "sloi">, Sched<[]>;
 def SROI : RVBShift_ri<0b00100, 0b101, OPC_OP_IMM, "sroi">, Sched<[]>;
@@ -405,6 +411,10 @@
 def GREVW  : ALUW_rr<0b0110100, 0b101, "grevw">, Sched<[]>;
 } // Predicates = [HasStdExtZbp, IsRV64]
 
+let Predicates = [HasStdExtZbp, IsRV64] in {
+def XPERMW : ALU_rr<0b0010100, 0b000, "xperm.w">, Sched<[]>;
+} // Predicates = [HasStdExtZbp, IsRV64]
+
 let Predicates = [HasStdExtZbp, IsRV64] in {
 def SLOIW  : RVBShiftW_ri<0b0010000, 0b001, OPC_OP_IMM_32, "sloiw">, Sched<[]>;
 def SROIW  : RVBShiftW_ri<0b0010000, 0b101, OPC_OP_IMM_32, "sroiw">, Sched<[]>;


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