[PATCH] D95218: [AArch64] Merge [US]MULL with half adds and subs into [US]ML[AS]L

Dave Green via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Jan 22 03:32:57 PST 2021


dmgreen added a comment.

Sounds good to me. Can you clean up the tests a little?



================
Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:4795
 
+// Additional patterns for [SU]ML[AS]L
+multiclass Neon_mul_acc_widen_patterns<SDPatternOperator opnode, SDPatternOperator vecopnode,
----------------
Maybe explain the reason for these patterns? That they are for when only the bottom half of the add is used.


================
Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:4803
+                            (i64 0))))),
+             (EXTRACT_SUBREG (v8i16 (INST8B
+                                     (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), V64:$Ra, dsub),
----------------
Can you line these up? I'm pretty sure it's off by a space.


================
Comment at: llvm/test/CodeGen/AArch64/mla_mls_merge.ll:3
+
+; Function Attrs: nofree nounwind uwtable
+define dso_local void @test_mla0(<8 x i8>* nocapture readonly %a, <8 x i8>* nocapture readonly %b, i16* nocapture %dest) local_unnamed_addr {
----------------
You can remove these.


================
Comment at: llvm/test/CodeGen/AArch64/mla_mls_merge.ll:4
+; Function Attrs: nofree nounwind uwtable
+define dso_local void @test_mla0(<8 x i8>* nocapture readonly %a, <8 x i8>* nocapture readonly %b, i16* nocapture %dest) local_unnamed_addr {
+entry:
----------------
Remove dso_local and local_unnamed_addr.


================
Comment at: llvm/test/CodeGen/AArch64/mla_mls_merge.ll:18
+  %4 = bitcast i16* %dest to <4 x i16>*
+  store <4 x i16> %vrshr_n6, <4 x i16>* %4, align 2
+  ret void
----------------
Hmm. These tests could probably be simplified, or simpler versions added. I don't think that the urshl/store is needed if the value is returned directly, and the loaded values could be arguments?

Can you also run update_llc_test_checks on it.


================
Comment at: llvm/test/CodeGen/AArch64/mla_mls_merge.ll:273
+
+; Function Attrs: nofree nosync nounwind readnone willreturn
+declare <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8>, <8 x i8>)
----------------
You can remove these too.


Repository:
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  https://reviews.llvm.org/D95218/new/

https://reviews.llvm.org/D95218



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