[PATCH] D95146: [RISCV] Make v extension imply zvamo, zvlsseg

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng added a comment.

> In the mean time I will park this change, and add 'v' implying its subfeatures in clang, since this would catch most cases we expect users to use (I don't think manually enabling features is a common use case). I can then later look at a more detailed/complete fix when enabling features directly with -mattr.

That's SGTM.

> @kito-cheng To clarify, if someone asks for e.g -march=rv32izvamo0p9, I enable 'v' because that's implied by zvamo, do we also enable zvlsseg, or does asking just for zvamo mean 'v+zvamo' but not 'v+zvamo+zvlsseg'/do I imply these features recursively?

In current GCC implementation, yes, `-march=rv32izvamo` will result `-march=rv32iv_zvamo_zvlsseg`, it's buggy work-around to me, but currently seems like no good choice here.

Related issue on v-spec: https://github.com/riscv/riscv-v-spec/issues/546


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https://reviews.llvm.org/D95146