[PATCH] D95214: fix a bug when llc -O0 vfmv.f.s.ll

[luxufan via Phabricator via llvm-commits]

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  The SUBREG_TO_REG opcode can't be eliminated when llc's optimize level is -O0. For the code show in below:
  ```
  define dso_local double @test(<vscale x 1 x double> %v) #0 {
  entry:
    %0 = call double @llvm.riscv.vfmv.f.s.f64.nxv1f64(<vscale x 1 x double> %v)
    ret double %0
  }
  ```

when I use llc -O0 to codegen this .ll file. The mir after PostRAPseudos pass is

  body:             |
    bb.0.entry:
      liveins: $v8, $x1
    
      $x2 = frame-setup ADDI $x2, -16
      CFI_INSTRUCTION def_cfa_offset 16
      SD killed $x1, $x2, 8 :: (store 8 into %stack.0)
      SD killed $x8, $x2, 0 :: (store 8 into %stack.1)
      CFI_INSTRUCTION offset $x1, -8
      CFI_INSTRUCTION offset $x8, -16
      $x8 = frame-setup ADDI $x2, 16
      CFI_INSTRUCTION def_cfa $x8, 0
      dead $x0 = PseudoVSETVLI killed $x0, 88, implicit-def $vl, implicit-def $vtype
      renamable $f0_f = PseudoVFMV_F_S_M1 killed renamable $v8, -1, implicit $vl, implicit $vtype
      $f10_f = FSGNJ_S killed $f0_f, killed $f0_f, implicit-def $f10_d
      $x8 = LD $x2, 0 :: (load 8 from %stack.1)
      $x1 = LD $x2, 8 :: (load 8 from %stack.0)
      $x2 = frame-destroy ADDI $x2, 16
      PseudoRET implicit killed $f10_d
  
  ...

The PostRVPseudos pass will lower the SUBREG_TO_REG to a instruciton of DstSubReg = COPY InsReg. So the
FSGNJ_S instruction appear. But the FSGNJ_S is the f32 register move instruction. Which is not correct for
f64 move.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D95214

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll

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