[PATCH] D95136: [X86] Fix tile config register spill issue.

[Pengfei Wang via Phabricator via llvm-commits]

pengfei added inline comments.


================
Comment at: llvm/lib/Target/X86/X86PreTileConfig.cpp:244
+    } else if (I->isCall()) {
+      if (std::next(I) != E)
+        WorkList.push(CallPointPair(LastAMX, I));
----------------
xiangzhangllvm wrote:
> If the call at the bottom of the BB, we may need insert tile_ld_config too.
Good catch! Thanks.


================
Comment at: llvm/lib/Target/X86/X86PreTileConfig.cpp:284
+    CPP.second++;
+    if (findAllSuccSlot(CPP, WorkList, LastAMXSet) && Call != MI)
+      CfgNeedInsert.insert(Call);
----------------
xiangzhangllvm wrote:
> xiangzhangllvm wrote:
> > xiangzhangllvm wrote:
> > > The Algorithm complexity is O(N*N)
> > > 
> > > The Algorithm complexity is O(N*N)
> > > 
> > 
> > 
> > The Algorithm complexity is O(N*N)
> I think we can do this in 1 DFS.
> 
> 
> > The Algorithm complexity is O(N*N)
> I think we can do this in 1 DFS.
> 

The Algorithm complexity is O(N) ideally. E.g. Each BB has at least one call. If not, the BB (and its successor) might be iterated more than once. I can improve it future.




Repository:
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  https://reviews.llvm.org/D95136/new/

https://reviews.llvm.org/D95136