[PATCH] D94749: [RISCV] Correct DWARF number for vector registers.

[Hsiangkai Wang via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG5d354220d44f: [RISCV] Correct DWARF number for vector registers. (authored by HsiangKai).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94749/new/

https://reviews.llvm.org/D94749

Files:
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td


Index: llvm/lib/Target/RISCV/RISCVRegisterInfo.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -411,7 +411,7 @@
 // Vector registers
 let RegAltNameIndices = [ABIRegAltName] in {
   foreach Index = 0-31 in {
-    def V#Index : RISCVReg<Index, "v"#Index, ["v"#Index]>, DwarfRegNum<[!add(Index, 64)]>;
+    def V#Index : RISCVReg<Index, "v"#Index, ["v"#Index]>, DwarfRegNum<[!add(Index, 96)]>;
   }
 
   foreach Index = [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22,


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